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From: "Steffen Görtz" <contrib@steffen-goertz.de>
To: qemu-devel@nongnu.org
Cc: "Stefan Hajnoczi" <stefanha@gmail.com>,
	"Joel Stanley" <joel@jms.id.au>,
	"Jim Mussared" <jim@groklearning.com>,
	"Julia Suvorova" <jusual@mail.ru>,
	"Steffen Görtz" <contrib@steffen-goertz.de>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"open list:ARM" <qemu-arm@nongnu.org>
Subject: [Qemu-devel] [RFC 4/8] arm: NRF51 Calculate peripheral id from base address
Date: Wed, 27 Jun 2018 09:33:47 +0200	[thread overview]
Message-ID: <20180627073351.856-5-contrib@steffen-goertz.de> (raw)
In-Reply-To: <20180627073351.856-1-contrib@steffen-goertz.de>

The base address determines a peripherals id, which identifies its
interrupt line, see NRF51 reference manual section 10 peripheral
interface. This little gem calculates the peripheral id based
on its base address.

Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de>
---
 hw/arm/nrf51_soc.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
index bfcacdf447..e93699a4b0 100644
--- a/hw/arm/nrf51_soc.c
+++ b/hw/arm/nrf51_soc.c
@@ -23,8 +23,6 @@
 
 #include "hw/arm/nrf51_soc.h"
 
-#define IOMEM_BASE      0x40000000
-#define IOMEM_SIZE      0x20000000
 
 #define FLASH_BASE      0x00000000
 
@@ -33,12 +31,19 @@
 
 #define SRAM_BASE       0x20000000
 
+#define IOMEM_BASE      0x40000000
+#define IOMEM_SIZE      0x20000000
+
 #define UART_BASE       0x40002000
 #define UART_SIZE       0x1000
 #define UART_INT        2
 
+#define RNG_BASE        0x4000D000
+
 #define PAGE_SIZE       1024
 
+#define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)
+
 
 struct {
   hwaddr ram_size;
@@ -177,7 +182,6 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
         return;
     }
 
-
     object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
     if (err) {
         error_propagate(errp, err);
@@ -204,7 +208,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);
     memory_region_add_subregion_overlap(&s->container, UART_BASE, mr, 0);
     qdev_connect_gpio_out_named(DEVICE(&s->uart), "irq", 0,
-            qdev_get_gpio_in(DEVICE(&s->armv7m), UART_INT));
+            qdev_get_gpio_in(DEVICE(&s->armv7m), BASE_TO_IRQ(UART_BASE)));
 
     /* STUB Peripherals */
     memory_region_init_io(&s->clock, NULL, &clock_ops, NULL, "nrf51_soc.clock", 0x1000);
-- 
2.17.1

  parent reply	other threads:[~2018-06-27  7:34 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-27  7:33 [Qemu-devel] [RFC 0/8] arm: Changes to Microbit Board and NRF51 SOC Steffen Görtz
2018-06-27  7:33 ` [Qemu-devel] [RFC 1/8] arm: NRF51/Microbit Memory container and SOC variants Steffen Görtz
2018-06-27  9:53   ` Stefan Hajnoczi
2018-06-27  7:33 ` [Qemu-devel] [RFC 2/8] arm: NRF51 Add unimplemented device for MMIO Steffen Görtz
2018-06-27  7:33 ` [Qemu-devel] [RFC 3/8] arm: NRF51 create UART in-place, error handling Steffen Görtz
2018-06-27  7:33 ` Steffen Görtz [this message]
2018-06-27  7:33 ` [Qemu-devel] [RFC 5/8] arm: Add NRF51 random number generator peripheral Steffen Görtz
2018-07-05 16:51   ` Peter Maydell
2018-07-05 17:19     ` Steffen Görtz
2018-06-27  7:33 ` [Qemu-devel] [RFC 6/8] arm: Add UICR/FICR handling to NRF51 SOC Steffen Görtz
2018-06-27  9:57   ` Stefan Hajnoczi
2018-06-27  7:33 ` [Qemu-devel] [RFC 7/8] arm: Add NRF51 SOC non-volatile memory controller Steffen Görtz
2018-06-27  7:33 ` [Qemu-devel] [RFC 8/8] arm: Instantiate NVMC in NRF51 Steffen Görtz
2018-06-27  9:46 ` [Qemu-devel] [RFC 0/8] arm: Changes to Microbit Board and NRF51 SOC Stefan Hajnoczi

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