From: "Steffen Görtz" <contrib@steffen-goertz.de>
To: qemu-devel@nongnu.org
Cc: "Stefan Hajnoczi" <stefanha@gmail.com>,
"Joel Stanley" <joel@jms.id.au>,
"Jim Mussared" <jim@groklearning.com>,
"Julia Suvorova" <jusual@mail.ru>,
"Steffen Görtz" <contrib@steffen-goertz.de>,
"Peter Maydell" <peter.maydell@linaro.org>,
"open list:ARM" <qemu-arm@nongnu.org>
Subject: [Qemu-devel] [RFC 8/8] arm: Instantiate NVMC in NRF51.
Date: Wed, 27 Jun 2018 09:33:51 +0200 [thread overview]
Message-ID: <20180627073351.856-9-contrib@steffen-goertz.de> (raw)
In-Reply-To: <20180627073351.856-1-contrib@steffen-goertz.de>
Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de>
---
hw/arm/nrf51_soc.c | 50 +++++++++++++++++++++++---------------
include/hw/arm/nrf51_soc.h | 3 ++-
2 files changed, 32 insertions(+), 21 deletions(-)
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
index 82e4c2d833..9ff622b792 100644
--- a/hw/arm/nrf51_soc.c
+++ b/hw/arm/nrf51_soc.c
@@ -40,6 +40,9 @@
#define UART_SIZE 0x1000
#define UART_INT 2
+#define NVMC_BASE 0x4001E000
+#define NVMC_SIZE 0x1000
+
#define RNG_BASE 0x4000D000
#define PAGE_SIZE 1024
@@ -182,23 +185,6 @@ static const MemoryRegionOps clock_ops = {
.write = clock_write
};
-static uint64_t nvmc_read(void *opaque, hwaddr addr, unsigned int size)
-{
- qemu_log_mask(LOG_TRACE, "%s: 0x%" HWADDR_PRIx " [%u]\n", __func__, addr, size);
- return 1;
-}
-
-static void nvmc_write(void *opaque, hwaddr addr, uint64_t data, unsigned int size)
-{
- qemu_log_mask(LOG_TRACE, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n", __func__, addr, data, size);
-}
-
-
-static const MemoryRegionOps nvmc_ops = {
- .read = nvmc_read,
- .write = nvmc_write
-};
-
static void nrf51_soc_init(Object *obj)
{
NRF51State *s = NRF51_SOC(obj);
@@ -223,6 +209,10 @@ static void nrf51_soc_init(Object *obj)
object_property_add_child(obj, "uart", OBJECT(&s->uart), &error_abort);
qdev_set_parent_bus(DEVICE(&s->uart), sysbus_get_default());
+ object_initialize(&s->nvmc, sizeof(s->nvmc), TYPE_NRF51_NVMC);
+ object_property_add_child(obj, "nvmc", OBJECT(&s->nvmc), &error_abort);
+ qdev_set_parent_bus(DEVICE(&s->nvmc), sysbus_get_default());
+
object_initialize(&s->rng, sizeof(s->rng), TYPE_NRF51_RNG);
object_property_add_child(obj, "rng", OBJECT(&s->rng), &error_abort);
qdev_set_parent_bus(DEVICE(&s->rng), sysbus_get_default());
@@ -309,6 +299,29 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
qdev_connect_gpio_out_named(DEVICE(&s->uart), "irq", 0,
qdev_get_gpio_in(DEVICE(&s->armv7m), BASE_TO_IRQ(UART_BASE)));
+ /* NVMC */
+ object_property_set_link(OBJECT(&s->nvmc), OBJECT(&s->container),
+ "memory", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ object_property_set_uint(OBJECT(&s->nvmc),
+ NRF51VariantAttributes[s->part_variant].flash_size, "code_size",
+ &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ object_property_set_bool(OBJECT(&s->nvmc), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+
+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvmc), 0);
+ memory_region_add_subregion_overlap(&s->container, NVMC_BASE, mr, 0);
+
/* RNG */
object_property_set_bool(OBJECT(&s->rng), true, "realized", &err);
if (err) {
@@ -324,9 +337,6 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
/* STUB Peripherals */
memory_region_init_io(&s->clock, NULL, &clock_ops, NULL, "nrf51_soc.clock", 0x1000);
memory_region_add_subregion_overlap(&s->container, IOMEM_BASE, &s->clock, -1);
-
- memory_region_init_io(&s->nvmc, NULL, &nvmc_ops, NULL, "nrf51_soc.nvmc", 0x1000);
- memory_region_add_subregion_overlap(&s->container, 0x4001E000, &s->nvmc, -1);
}
static Property nrf51_soc_properties[] = {
diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h
index 35dd71c3db..70d9f5863c 100644
--- a/include/hw/arm/nrf51_soc.h
+++ b/include/hw/arm/nrf51_soc.h
@@ -15,6 +15,7 @@
#include "hw/arm/armv7m.h"
#include "hw/misc/unimp.h"
#include "hw/char/nrf51_uart.h"
+#include "hw/nvram/nrf51_nvmc.h"
#include "hw/misc/nrf51_rng.h"
@@ -32,6 +33,7 @@ typedef struct NRF51State {
UnimplementedDeviceState mmio;
Nrf51UART uart;
+ Nrf51NVMCState nvmc;
Nrf51RNGState rng;
MemoryRegion container;
@@ -40,7 +42,6 @@ typedef struct NRF51State {
MemoryRegion ficr;
MemoryRegion uicr;
MemoryRegion clock;
- MemoryRegion nvmc;
/* Properties */
int32_t part_variant;
--
2.17.1
next prev parent reply other threads:[~2018-06-27 7:34 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-27 7:33 [Qemu-devel] [RFC 0/8] arm: Changes to Microbit Board and NRF51 SOC Steffen Görtz
2018-06-27 7:33 ` [Qemu-devel] [RFC 1/8] arm: NRF51/Microbit Memory container and SOC variants Steffen Görtz
2018-06-27 9:53 ` Stefan Hajnoczi
2018-06-27 7:33 ` [Qemu-devel] [RFC 2/8] arm: NRF51 Add unimplemented device for MMIO Steffen Görtz
2018-06-27 7:33 ` [Qemu-devel] [RFC 3/8] arm: NRF51 create UART in-place, error handling Steffen Görtz
2018-06-27 7:33 ` [Qemu-devel] [RFC 4/8] arm: NRF51 Calculate peripheral id from base address Steffen Görtz
2018-06-27 7:33 ` [Qemu-devel] [RFC 5/8] arm: Add NRF51 random number generator peripheral Steffen Görtz
2018-07-05 16:51 ` Peter Maydell
2018-07-05 17:19 ` Steffen Görtz
2018-06-27 7:33 ` [Qemu-devel] [RFC 6/8] arm: Add UICR/FICR handling to NRF51 SOC Steffen Görtz
2018-06-27 9:57 ` Stefan Hajnoczi
2018-06-27 7:33 ` [Qemu-devel] [RFC 7/8] arm: Add NRF51 SOC non-volatile memory controller Steffen Görtz
2018-06-27 7:33 ` Steffen Görtz [this message]
2018-06-27 9:46 ` [Qemu-devel] [RFC 0/8] arm: Changes to Microbit Board and NRF51 SOC Stefan Hajnoczi
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