[Qemu-devel] [PULL 0/7] riscv-pull queue

[Qemu-devel] [PULL 0/7] riscv-pull queue

[Alistair Francis]

The following changes since commit 00928a421d47f49691cace1207481b7aad31b1f1:

  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180626' into staging (2018-06-26 18:23:49 +0100)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-pull-20180627

for you to fetch changes up to e5f5e16b67dc8a342f937bc00ebb2a6475e35050:

  hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device (2018-06-27 10:35:19 -0700)

----------------------------------------------------------------
RISC-V: SoCify SiFive boards and connect GEM

This series has three tasks:
 1. To convert the SiFive U and E machines into SoCs and boards
 2. To connect the Cadence GEM device to the SiFive U board
 3. Fix some device tree problems with the SiFive U board

After this series the SiFive E and U boards have their SoCs split into
seperate QEMU objects, which can be used on future boards if desired.

The RISC-V Virt and Spike boards have not been converted. They haven't
been converted as they aren't physical boards, so it doesn't make a
whole lot of sense to split them into an SoC and board. The only
disadvantage with this is that they now differ to the SiFive boards.

This series also connect the Cadence GEM device to the SiFive U board.
There are some interrupt line changes requried before this is possible.

----------------------------------------------------------------
Alistair Francis (7):
      hw/riscv/sifive_u: Create a SiFive U SoC object
      hw/riscv/sifive_e: Create a SiFive E SoC object
      hw/riscv/sifive_plic: Use gpios instead of irqs
      hw/riscv/sifive_u: Set the soc device tree node as a simple-bus
      hw/riscv/sifive_u: Set the interrupt controler number of interrupts
      hw/riscv/sifive_u: Move the uart device tree node under /soc/
      hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device

 default-configs/riscv32-softmmu.mak |   3 +-
 default-configs/riscv64-softmmu.mak |   3 +-
 hw/riscv/sifive_e.c                 | 102 +++++++++++++++++-------
 hw/riscv/sifive_plic.c              |   6 +-
 hw/riscv/sifive_u.c                 | 151 +++++++++++++++++++++++++++++-------
 hw/riscv/virt.c                     |   4 +-
 include/hw/riscv/sifive_e.h         |  16 +++-
 include/hw/riscv/sifive_plic.h      |   1 -
 include/hw/riscv/sifive_u.h         |  25 +++++-
 9 files changed, 241 insertions(+), 70 deletions(-)

[Qemu-devel] [PULL 1/7] hw/riscv/sifive_u: Create a SiFive U SoC object

[Alistair Francis]

Create a SiFive Unleashed U54 SoC and use that in the sifive_u machine.

We leave the SoC, RAM, device tree and reset/fdt loading as part of the
machine. All the other device creation has been moved to the SoC.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
---
 hw/riscv/sifive_u.c         | 90 ++++++++++++++++++++++++++++---------
 include/hw/riscv/sifive_u.h | 16 ++++++-
 2 files changed, 82 insertions(+), 24 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index c05dcbba95..45b6aeb36b 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -116,10 +116,10 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
 
-    for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
+    for (cpu = s->soc.cpus.num_harts - 1; cpu >= 0; cpu--) {
         nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
         char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
-        char *isa = riscv_isa_string(&s->soc.harts[cpu]);
+        char *isa = riscv_isa_string(&s->soc.cpus.harts[cpu]);
         qemu_fdt_add_subnode(fdt, nodename);
         qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
                               SIFIVE_U_CLOCK_FREQ);
@@ -140,8 +140,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
         g_free(nodename);
     }
 
-    cells =  g_new0(uint32_t, s->soc.num_harts * 4);
-    for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
+    cells =  g_new0(uint32_t, s->soc.cpus.num_harts * 4);
+    for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) {
         nodename =
             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
@@ -159,12 +159,12 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
         0x0, memmap[SIFIVE_U_CLINT].base,
         0x0, memmap[SIFIVE_U_CLINT].size);
     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
-        cells, s->soc.num_harts * sizeof(uint32_t) * 4);
+        cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4);
     g_free(cells);
     g_free(nodename);
 
-    cells =  g_new0(uint32_t, s->soc.num_harts * 4);
-    for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
+    cells =  g_new0(uint32_t, s->soc.cpus.num_harts * 4);
+    for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) {
         nodename =
             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
@@ -181,7 +181,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
-        cells, s->soc.num_harts * sizeof(uint32_t) * 4);
+        cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4);
     qemu_fdt_setprop_cells(fdt, nodename, "reg",
         0x0, memmap[SIFIVE_U_PLIC].base,
         0x0, memmap[SIFIVE_U_PLIC].size);
@@ -217,17 +217,12 @@ static void riscv_sifive_u_init(MachineState *machine)
     SiFiveUState *s = g_new0(SiFiveUState, 1);
     MemoryRegion *system_memory = get_system_memory();
     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
-    MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
     int i;
 
-    /* Initialize SOC */
-    object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY);
+    /* Initialize SoC */
+    object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_U_SOC);
     object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
                               &error_abort);
-    object_property_set_str(OBJECT(&s->soc), SIFIVE_U_CPU, "cpu-type",
-                            &error_abort);
-    object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
-                            &error_abort);
     object_property_set_bool(OBJECT(&s->soc), true, "realized",
                             &error_abort);
 
@@ -235,17 +230,11 @@ static void riscv_sifive_u_init(MachineState *machine)
     memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
                            machine->ram_size, &error_fatal);
     memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
-        main_mem);
+                                main_mem);
 
     /* create device tree */
     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
 
-    /* boot rom */
-    memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom",
-                           memmap[SIFIVE_U_MROM].size, &error_fatal);
-    memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
-                                mask_rom);
-
     if (machine->kernel_filename) {
         load_kernel(machine->kernel_filename);
     }
@@ -284,6 +273,39 @@ static void riscv_sifive_u_init(MachineState *machine)
     rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
                           memmap[SIFIVE_U_MROM].base + sizeof(reset_vec),
                           &address_space_memory);
+}
+
+static void riscv_sifive_u_soc_init(Object *obj)
+{
+    const struct MemmapEntry *memmap = sifive_u_memmap;
+
+    SiFiveUSoCState *s = RISCV_U_SOC(obj);
+    MemoryRegion *system_memory = get_system_memory();
+    MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
+
+    object_initialize(&s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY);
+    object_property_add_child(obj, "cpus", OBJECT(&s->cpus),
+                              &error_abort);
+    object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type",
+                            &error_abort);
+    object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",
+                            &error_abort);
+
+    /* boot rom */
+    memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom",
+                           memmap[SIFIVE_U_MROM].size, &error_fatal);
+    memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
+                                mask_rom);
+}
+
+static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
+{
+    SiFiveUSoCState *s = RISCV_U_SOC(dev);
+    const struct MemmapEntry *memmap = sifive_u_memmap;
+    MemoryRegion *system_memory = get_system_memory();
+
+    object_property_set_bool(OBJECT(&s->cpus), true, "realized",
+                             &error_abort);
 
     /* MMIO */
     s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
@@ -314,3 +336,27 @@ static void riscv_sifive_u_machine_init(MachineClass *mc)
 }
 
 DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
+
+static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    dc->realize = riscv_sifive_u_soc_realize;
+    /* Reason: Uses serial_hds in realize function, thus can't be used twice */
+    dc->user_creatable = false;
+}
+
+static const TypeInfo riscv_sifive_u_soc_type_info = {
+    .name = TYPE_RISCV_U_SOC,
+    .parent = TYPE_DEVICE,
+    .instance_size = sizeof(SiFiveUSoCState),
+    .instance_init = riscv_sifive_u_soc_init,
+    .class_init = riscv_sifive_u_soc_class_init,
+};
+
+static void riscv_sifive_u_soc_register_types(void)
+{
+    type_register_static(&riscv_sifive_u_soc_type_info);
+}
+
+type_init(riscv_sifive_u_soc_register_types)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 94a390566e..49f1946539 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -19,13 +19,25 @@
 #ifndef HW_SIFIVE_U_H
 #define HW_SIFIVE_U_H
 
-typedef struct SiFiveUState {
+#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
+#define RISCV_U_SOC(obj) \
+    OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC)
+
+typedef struct SiFiveUSoCState {
     /*< private >*/
     SysBusDevice parent_obj;
 
     /*< public >*/
-    RISCVHartArrayState soc;
+    RISCVHartArrayState cpus;
     DeviceState *plic;
+} SiFiveUSoCState;
+
+typedef struct SiFiveUState {
+    /*< private >*/
+    SysBusDevice parent_obj;
+
+    /*< public >*/
+    SiFiveUSoCState soc;
     void *fdt;
     int fdt_size;
 } SiFiveUState;
-- 
2.17.1

[Qemu-devel] [PULL 2/7] hw/riscv/sifive_e: Create a SiFive E SoC object

[Alistair Francis]

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
---
 hw/riscv/sifive_e.c         | 97 +++++++++++++++++++++++++++----------
 include/hw/riscv/sifive_e.h | 16 +++++-
 2 files changed, 86 insertions(+), 27 deletions(-)

diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index e4ecb7aa4b..384b456540 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -102,18 +102,12 @@ static void riscv_sifive_e_init(MachineState *machine)
     SiFiveEState *s = g_new0(SiFiveEState, 1);
     MemoryRegion *sys_mem = get_system_memory();
     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
-    MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
-    MemoryRegion *xip_mem = g_new(MemoryRegion, 1);
     int i;
 
-    /* Initialize SOC */
-    object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY);
+    /* Initialize SoC */
+    object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_E_SOC);
     object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
                               &error_abort);
-    object_property_set_str(OBJECT(&s->soc), SIFIVE_E_CPU, "cpu-type",
-                            &error_abort);
-    object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
-                            &error_abort);
     object_property_set_bool(OBJECT(&s->soc), true, "realized",
                             &error_abort);
 
@@ -123,11 +117,57 @@ static void riscv_sifive_e_init(MachineState *machine)
     memory_region_add_subregion(sys_mem,
         memmap[SIFIVE_E_DTIM].base, main_mem);
 
+    /* Mask ROM reset vector */
+    uint32_t reset_vec[2] = {
+        0x204002b7,        /* 0x1000: lui     t0,0x20400 */
+        0x00028067,        /* 0x1004: jr      t0 */
+    };
+
+    /* copy in the reset vector in little_endian byte order */
+    for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
+        reset_vec[i] = cpu_to_le32(reset_vec[i]);
+    }
+    rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
+                          memmap[SIFIVE_E_MROM].base, &address_space_memory);
+
+    if (machine->kernel_filename) {
+        load_kernel(machine->kernel_filename);
+    }
+}
+
+static void riscv_sifive_e_soc_init(Object *obj)
+{
+    const struct MemmapEntry *memmap = sifive_e_memmap;
+
+    SiFiveESoCState *s = RISCV_E_SOC(obj);
+    MemoryRegion *sys_mem = get_system_memory();
+    MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
+
+    object_initialize(&s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY);
+    object_property_add_child(obj, "cpus", OBJECT(&s->cpus),
+                              &error_abort);
+    object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type",
+                            &error_abort);
+    object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",
+                            &error_abort);
+
     /* Mask ROM */
     memory_region_init_rom(mask_rom, NULL, "riscv.sifive.e.mrom",
         memmap[SIFIVE_E_MROM].size, &error_fatal);
     memory_region_add_subregion(sys_mem,
         memmap[SIFIVE_E_MROM].base, mask_rom);
+}
+
+static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
+{
+    const struct MemmapEntry *memmap = sifive_e_memmap;
+
+    SiFiveESoCState *s = RISCV_E_SOC(dev);
+    MemoryRegion *sys_mem = get_system_memory();
+    MemoryRegion *xip_mem = g_new(MemoryRegion, 1);
+
+    object_property_set_bool(OBJECT(&s->cpus), true, "realized",
+                            &error_abort);
 
     /* MMIO */
     s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base,
@@ -171,23 +211,6 @@ static void riscv_sifive_e_init(MachineState *machine)
         memmap[SIFIVE_E_XIP].size, &error_fatal);
     memory_region_set_readonly(xip_mem, true);
     memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base, xip_mem);
-
-    /* Mask ROM reset vector */
-    uint32_t reset_vec[2] = {
-        0x204002b7,        /* 0x1000: lui     t0,0x20400 */
-        0x00028067,        /* 0x1004: jr      t0 */
-    };
-
-    /* copy in the reset vector in little_endian byte order */
-    for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
-        reset_vec[i] = cpu_to_le32(reset_vec[i]);
-    }
-    rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
-                          memmap[SIFIVE_E_MROM].base, &address_space_memory);
-
-    if (machine->kernel_filename) {
-        load_kernel(machine->kernel_filename);
-    }
 }
 
 static void riscv_sifive_e_machine_init(MachineClass *mc)
@@ -198,3 +221,27 @@ static void riscv_sifive_e_machine_init(MachineClass *mc)
 }
 
 DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
+
+static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    dc->realize = riscv_sifive_e_soc_realize;
+    /* Reason: Uses serial_hds in realize function, thus can't be used twice */
+    dc->user_creatable = false;
+}
+
+static const TypeInfo riscv_sifive_e_soc_type_info = {
+    .name = TYPE_RISCV_E_SOC,
+    .parent = TYPE_DEVICE,
+    .instance_size = sizeof(SiFiveESoCState),
+    .instance_init = riscv_sifive_e_soc_init,
+    .class_init = riscv_sifive_e_soc_class_init,
+};
+
+static void riscv_sifive_e_soc_register_types(void)
+{
+    type_register_static(&riscv_sifive_e_soc_type_info);
+}
+
+type_init(riscv_sifive_e_soc_register_types)
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index 12ad6d2ebb..7b6d8aed96 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -19,13 +19,25 @@
 #ifndef HW_SIFIVE_E_H
 #define HW_SIFIVE_E_H
 
-typedef struct SiFiveEState {
+#define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
+#define RISCV_E_SOC(obj) \
+    OBJECT_CHECK(SiFiveESoCState, (obj), TYPE_RISCV_E_SOC)
+
+typedef struct SiFiveESoCState {
     /*< private >*/
     SysBusDevice parent_obj;
 
     /*< public >*/
-    RISCVHartArrayState soc;
+    RISCVHartArrayState cpus;
     DeviceState *plic;
+} SiFiveESoCState;
+
+typedef struct SiFiveEState {
+    /*< private >*/
+    SysBusDevice parent_obj;
+
+    /*< public >*/
+    SiFiveESoCState soc;
 } SiFiveEState;
 
 enum {
-- 
2.17.1

[Qemu-devel] [PULL 3/7] hw/riscv/sifive_plic: Use gpios instead of irqs

[Alistair Francis]

Instead of creating the interrupt in lines with qemu_allocate_irq() use
qdev_init_gpio_in() as this gives us the ability to use the qdev*gpio*()
helpers later on.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Michael Clark <mjc@sifive.com>
---
 hw/riscv/sifive_e.c            | 5 +++--
 hw/riscv/sifive_plic.c         | 6 +-----
 hw/riscv/sifive_u.c            | 5 +++--
 hw/riscv/virt.c                | 4 ++--
 include/hw/riscv/sifive_plic.h | 1 -
 5 files changed, 9 insertions(+), 12 deletions(-)

diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 384b456540..006703163b 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -190,13 +190,14 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
     sifive_mmio_emulate(sys_mem, "riscv.sifive.e.gpio0",
         memmap[SIFIVE_E_GPIO0].base, memmap[SIFIVE_E_GPIO0].size);
     sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base,
-        serial_hd(0), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_E_UART0_IRQ]);
+        serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
     sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0",
         memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size);
     sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0",
         memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size);
     /* sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base,
-        serial_hd(1), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_E_UART1_IRQ]); */
+        serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic),
+                                       SIFIVE_E_UART1_IRQ)); */
     sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1",
         memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size);
     sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1",
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index 874de2ebaf..a91aeb97ab 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -435,7 +435,6 @@ static void sifive_plic_irq_request(void *opaque, int irq, int level)
 static void sifive_plic_realize(DeviceState *dev, Error **errp)
 {
     SiFivePLICState *plic = SIFIVE_PLIC(dev);
-    int i;
 
     memory_region_init_io(&plic->mmio, OBJECT(dev), &sifive_plic_ops, plic,
                           TYPE_SIFIVE_PLIC, plic->aperture_size);
@@ -448,10 +447,7 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
     plic->claimed = g_new0(uint32_t, plic->bitfield_words);
     plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
-    plic->irqs = g_new0(qemu_irq, plic->num_sources + 1);
-    for (i = 0; i <= plic->num_sources; i++) {
-        plic->irqs[i] = qemu_allocate_irq(sifive_plic_irq_request, plic, i);
-    }
+    qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
 }
 
 static void sifive_plic_class_init(ObjectClass *klass, void *data)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 45b6aeb36b..3883d7ff9c 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -320,9 +320,10 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
         SIFIVE_U_PLIC_CONTEXT_STRIDE,
         memmap[SIFIVE_U_PLIC].size);
     sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
-        serial_hd(0), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART0_IRQ]);
+        serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
     /* sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
-        serial_hd(1), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART1_IRQ]); */
+        serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic),
+                                       SIFIVE_U_UART1_IRQ)); */
     sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
         memmap[SIFIVE_U_CLINT].size, smp_cpus,
         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index ad03113e0f..bdd75722eb 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -379,11 +379,11 @@ static void riscv_virt_board_init(MachineState *machine)
     for (i = 0; i < VIRTIO_COUNT; i++) {
         sysbus_create_simple("virtio-mmio",
             memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
-            SIFIVE_PLIC(s->plic)->irqs[VIRTIO_IRQ + i]);
+            qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
     }
 
     serial_mm_init(system_memory, memmap[VIRT_UART0].base,
-        0, SIFIVE_PLIC(s->plic)->irqs[UART0_IRQ], 399193,
+        0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
         serial_hd(0), DEVICE_LITTLE_ENDIAN);
 }
 
diff --git a/include/hw/riscv/sifive_plic.h b/include/hw/riscv/sifive_plic.h
index 11a5a98df1..2f2af7e686 100644
--- a/include/hw/riscv/sifive_plic.h
+++ b/include/hw/riscv/sifive_plic.h
@@ -56,7 +56,6 @@ typedef struct SiFivePLICState {
     uint32_t *claimed;
     uint32_t *enable;
     QemuMutex lock;
-    qemu_irq *irqs;
 
     /* config */
     char *hart_config;
-- 
2.17.1

[Qemu-devel] [PULL 4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus

[Alistair Francis]

To allow Linux to ennumerate devices on the /soc/ node set it as a
"simple-bus".

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
---
 hw/riscv/sifive_u.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 3883d7ff9c..f438a72c27 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -97,7 +97,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
 
     qemu_fdt_add_subnode(fdt, "/soc");
     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
-    qemu_fdt_setprop_string(fdt, "/soc", "compatible", "ucbbar,spike-bare-soc");
+    qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
 
-- 
2.17.1

[Qemu-devel] [PULL 5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts

[Alistair Francis]

Set the interrupt-controller ndev to the correct number taken from the
HiFive Unleashed board.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
---
 hw/riscv/sifive_u.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index f438a72c27..f71527eaff 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -187,7 +187,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
         0x0, memmap[SIFIVE_U_PLIC].size);
     qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
     qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
-    qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 4);
+    qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
     qemu_fdt_setprop_cells(fdt, nodename, "phandle", 2);
     qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", 2);
     plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
-- 
2.17.1

[Qemu-devel] [PULL 6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/

[Alistair Francis]

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
---
 hw/riscv/sifive_u.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index f71527eaff..46459cd368 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -194,7 +194,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
     g_free(cells);
     g_free(nodename);
 
-    nodename = g_strdup_printf("/uart@%lx",
+    nodename = g_strdup_printf("/soc/uart@%lx",
         (long)memmap[SIFIVE_U_UART0].base);
     qemu_fdt_add_subnode(fdt, nodename);
     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
-- 
2.17.1

[Qemu-devel] [PULL 7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device

[Alistair Francis]

Connect the Cadence GEM ethernet device. This also requires us to
expose the plic interrupt lines.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
---
 default-configs/riscv32-softmmu.mak |  3 +-
 default-configs/riscv64-softmmu.mak |  3 +-
 hw/riscv/sifive_u.c                 | 50 +++++++++++++++++++++++++++++
 include/hw/riscv/sifive_u.h         |  9 ++++--
 4 files changed, 61 insertions(+), 4 deletions(-)

diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak
index 20e670d99c..7a003eb5e2 100644
--- a/default-configs/riscv32-softmmu.mak
+++ b/default-configs/riscv32-softmmu.mak
@@ -2,4 +2,5 @@
 
 CONFIG_SERIAL=y
 CONFIG_VIRTIO_MMIO=y
-include virtio.mak
+CONFIG_VIRTIO=y
+CONFIG_CADENCE=y
diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak
index 20e670d99c..7a003eb5e2 100644
--- a/default-configs/riscv64-softmmu.mak
+++ b/default-configs/riscv64-softmmu.mak
@@ -2,4 +2,5 @@
 
 CONFIG_SERIAL=y
 CONFIG_VIRTIO_MMIO=y
-include virtio.mak
+CONFIG_VIRTIO=y
+CONFIG_CADENCE=y
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 46459cd368..1a06384367 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -60,8 +60,11 @@ static const struct MemmapEntry {
     [SIFIVE_U_UART0] =    { 0x10013000,     0x1000 },
     [SIFIVE_U_UART1] =    { 0x10023000,     0x1000 },
     [SIFIVE_U_DRAM] =     { 0x80000000,        0x0 },
+    [SIFIVE_U_GEM] =      { 0x100900FC,     0x2000 },
 };
 
+#define GEM_REVISION        0x10070109
+
 static uint64_t load_kernel(const char *kernel_filename)
 {
     uint64_t kernel_entry, kernel_high;
@@ -194,6 +197,27 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
     g_free(cells);
     g_free(nodename);
 
+    nodename = g_strdup_printf("/soc/ethernet@%lx",
+        (long)memmap[SIFIVE_U_GEM].base);
+    qemu_fdt_add_subnode(fdt, nodename);
+    qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb");
+    qemu_fdt_setprop_cells(fdt, nodename, "reg",
+        0x0, memmap[SIFIVE_U_GEM].base,
+        0x0, memmap[SIFIVE_U_GEM].size);
+    qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
+    qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
+    qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
+    qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
+    qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 1);
+    qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0);
+    g_free(nodename);
+
+    nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
+        (long)memmap[SIFIVE_U_GEM].base);
+    qemu_fdt_add_subnode(fdt, nodename);
+    qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0);
+    g_free(nodename);
+
     nodename = g_strdup_printf("/soc/uart@%lx",
         (long)memmap[SIFIVE_U_UART0].base);
     qemu_fdt_add_subnode(fdt, nodename);
@@ -296,6 +320,9 @@ static void riscv_sifive_u_soc_init(Object *obj)
                            memmap[SIFIVE_U_MROM].size, &error_fatal);
     memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
                                 mask_rom);
+
+    object_initialize(&s->gem, sizeof(s->gem), TYPE_CADENCE_GEM);
+    qdev_set_parent_bus(DEVICE(&s->gem), sysbus_get_default());
 }
 
 static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
@@ -303,6 +330,10 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
     SiFiveUSoCState *s = RISCV_U_SOC(dev);
     const struct MemmapEntry *memmap = sifive_u_memmap;
     MemoryRegion *system_memory = get_system_memory();
+    qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
+    int i;
+    Error *err = NULL;
+    NICInfo *nd = &nd_table[0];
 
     object_property_set_bool(OBJECT(&s->cpus), true, "realized",
                              &error_abort);
@@ -327,6 +358,25 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
     sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
         memmap[SIFIVE_U_CLINT].size, smp_cpus,
         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
+
+    for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
+        plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
+    }
+
+    if (nd->used) {
+        qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
+        qdev_set_nic_properties(DEVICE(&s->gem), nd);
+    }
+    object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision",
+                            &error_abort);
+    object_property_set_bool(OBJECT(&s->gem), true, "realized", &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
+                       plic_gpios[SIFIVE_U_GEM_IRQ]);
 }
 
 static void riscv_sifive_u_machine_init(MachineClass *mc)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 49f1946539..e8b4d9ffa3 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -19,6 +19,8 @@
 #ifndef HW_SIFIVE_U_H
 #define HW_SIFIVE_U_H
 
+#include "hw/net/cadence_gem.h"
+
 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
 #define RISCV_U_SOC(obj) \
     OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC)
@@ -30,6 +32,7 @@ typedef struct SiFiveUSoCState {
     /*< public >*/
     RISCVHartArrayState cpus;
     DeviceState *plic;
+    CadenceGEMState gem;
 } SiFiveUSoCState;
 
 typedef struct SiFiveUState {
@@ -49,12 +52,14 @@ enum {
     SIFIVE_U_PLIC,
     SIFIVE_U_UART0,
     SIFIVE_U_UART1,
-    SIFIVE_U_DRAM
+    SIFIVE_U_DRAM,
+    SIFIVE_U_GEM
 };
 
 enum {
     SIFIVE_U_UART0_IRQ = 3,
-    SIFIVE_U_UART1_IRQ = 4
+    SIFIVE_U_UART1_IRQ = 4,
+    SIFIVE_U_GEM_IRQ = 0x35
 };
 
 enum {
-- 
2.17.1

Re: [Qemu-devel] [PULL 0/7] riscv-pull queue

[Peter Maydell]

On 27 June 2018 at 18:44, Alistair Francis <alistair.francis@wdc.com> wrote:
> The following changes since commit 00928a421d47f49691cace1207481b7aad31b1f1:
>
>   Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180626' into staging (2018-06-26 18:23:49 +0100)
>
> are available in the Git repository at:
>
>   git@github.com:alistair23/qemu.git tags/pull-riscv-pull-20180627
>
> for you to fetch changes up to e5f5e16b67dc8a342f937bc00ebb2a6475e35050:
>
>   hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device (2018-06-27 10:35:19 -0700)
>

Something strange is up with the key used to sign this:

$ gpg --recv-keys 7048B74B4C1B39E4
gpg: requesting key 0x7048B74B4C1B39E4 from hkp server keys.gnupg.net
gpg: key 0xE48E3BC2C123ED93: no valid user IDs
gpg: this may be caused by a missing self-signature
gpg: Total number processed: 1
gpg:           w/o user IDs: 1

thanks
-- PMM

Re: [Qemu-devel] [PULL 0/7] riscv-pull queue

[Philippe Mathieu-Daudé]

On 06/28/2018 01:52 PM, Peter Maydell wrote:
> On 27 June 2018 at 18:44, Alistair Francis <alistair.francis@wdc.com> wrote:
>> The following changes since commit 00928a421d47f49691cace1207481b7aad31b1f1:
>>
>>   Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180626' into staging (2018-06-26 18:23:49 +0100)
>>
>> are available in the Git repository at:
>>
>>   git@github.com:alistair23/qemu.git tags/pull-riscv-pull-20180627
>>
>> for you to fetch changes up to e5f5e16b67dc8a342f937bc00ebb2a6475e35050:
>>
>>   hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device (2018-06-27 10:35:19 -0700)
>>
> 
> Something strange is up with the key used to sign this:
> 
> $ gpg --recv-keys 7048B74B4C1B39E4
> gpg: requesting key 0x7048B74B4C1B39E4 from hkp server keys.gnupg.net
> gpg: key 0xE48E3BC2C123ED93: no valid user IDs
> gpg: this may be caused by a missing self-signature
> gpg: Total number processed: 1
> gpg:           w/o user IDs: 1

It seems the SKS keyserver pool is having some problem:
https://sks-keyservers.net/status/

$ host keys.gnupg.net
keys.gnupg.net is an alias for hkps.pool.sks-keyservers.net.
...
hkps.pool.sks-keyservers.net has address 18.191.65.131
hkps.pool.sks-keyservers.net has address 37.191.226.104
...

Except these 2 IP, all other failed via hkp or http (as of tod:

The server is temporarily unable to service your request due to
maintenance downtime or capacity problems. Please try again later.

Also:

Proxy Error
The proxy server received an invalid response from an upstream server.
The proxy server could not handle the request GET /pks/lookup.
Reason: Error reading from remote server

$ gpg --keyserver hkp://18.191.65.131 --recv-keys 7048B74B4C1B39E4
gpg: key E48E3BC2C123ED93: public key "Alistair Francis
<alistair@alistair23.me>" imported
gpg: marginals needed: 3  completes needed: 1  trust model: pgp
gpg: depth: 0  valid:   4  signed:   3  trust: 0-, 0q, 0n, 0m, 0f, 4u
gpg: depth: 1  valid:   3  signed:  18  trust: 0-, 0q, 0n, 0m, 3f, 0u
gpg: depth: 2  valid:  16  signed:   6  trust: 10-, 6q, 0n, 0m, 0f, 0u
gpg: next trustdb check due at 2018-09-03
gpg: Total number processed: 1

$ git tag -v pull-riscv-pull-20180627
object e5f5e16b67dc8a342f937bc00ebb2a6475e35050
type commit
tag pull-riscv-pull-20180627
tagger Alistair Francis <alistair.francis@wdc.com> 1530121274 -0700
gpg: Signature made Wed 27 Jun 2018 02:41:26 PM -03
gpg:                using RSA key 100E2F7FE47ABA5024FF1B5B7048B74B4C1B39E4
gpg: Good signature from "Alistair Francis <alistair@alistair23.me>"
gpg:                 aka "Alistair Francis <alistair23@gmail.com>"
Primary key fingerprint: 29E0 5927 63B1 DA8C 8399  75FE E48E 3BC2 C123 ED93
     Subkey fingerprint: 100E 2F7F E47A BA50 24FF  1B5B 7048 B74B 4C1B 39E4

Re: [Qemu-devel] [PULL 0/7] riscv-pull queue

[Peter Maydell]

On 28 June 2018 at 22:35, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> On 06/28/2018 01:52 PM, Peter Maydell wrote:
>> On 27 June 2018 at 18:44, Alistair Francis <alistair.francis@wdc.com> wrote:
>>> The following changes since commit 00928a421d47f49691cace1207481b7aad31b1f1:
>>>
>>>   Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180626' into staging (2018-06-26 18:23:49 +0100)
>>>
>>> are available in the Git repository at:
>>>
>>>   git@github.com:alistair23/qemu.git tags/pull-riscv-pull-20180627
>>>
>>> for you to fetch changes up to e5f5e16b67dc8a342f937bc00ebb2a6475e35050:
>>>
>>>   hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device (2018-06-27 10:35:19 -0700)
>>>
>>
>> Something strange is up with the key used to sign this:
>>
>> $ gpg --recv-keys 7048B74B4C1B39E4
>> gpg: requesting key 0x7048B74B4C1B39E4 from hkp server keys.gnupg.net
>> gpg: key 0xE48E3BC2C123ED93: no valid user IDs
>> gpg: this may be caused by a missing self-signature
>> gpg: Total number processed: 1
>> gpg:           w/o user IDs: 1
>
> It seems the SKS keyserver pool is having some problem:
> https://sks-keyservers.net/status/

> The server is temporarily unable to service your request due to
> maintenance downtime or capacity problems. Please try again later.

Hmm, there does seem to be something up with the pool. On
the other hand:

> $ gpg --keyserver hkp://18.191.65.131 --recv-keys 7048B74B4C1B39E4

This command with this specific server doesn't work for me
(fails the same way with the "no valid user IDs" message),
and using keyserver.ubuntu.com (which seems otherwise fine)
also fails that way...

thanks
-- PMM

Re: [Qemu-devel] [PULL 0/7] riscv-pull queue

[Alistair Francis]

On Fri, Jun 29, 2018 at 2:41 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 28 June 2018 at 22:35, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>> On 06/28/2018 01:52 PM, Peter Maydell wrote:
>>> On 27 June 2018 at 18:44, Alistair Francis <alistair.francis@wdc.com> wrote:
>>>> The following changes since commit 00928a421d47f49691cace1207481b7aad31b1f1:
>>>>
>>>>   Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180626' into staging (2018-06-26 18:23:49 +0100)
>>>>
>>>> are available in the Git repository at:
>>>>
>>>>   git@github.com:alistair23/qemu.git tags/pull-riscv-pull-20180627
>>>>
>>>> for you to fetch changes up to e5f5e16b67dc8a342f937bc00ebb2a6475e35050:
>>>>
>>>>   hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device (2018-06-27 10:35:19 -0700)
>>>>
>>>
>>> Something strange is up with the key used to sign this:
>>>
>>> $ gpg --recv-keys 7048B74B4C1B39E4
>>> gpg: requesting key 0x7048B74B4C1B39E4 from hkp server keys.gnupg.net
>>> gpg: key 0xE48E3BC2C123ED93: no valid user IDs
>>> gpg: this may be caused by a missing self-signature
>>> gpg: Total number processed: 1
>>> gpg:           w/o user IDs: 1
>>
>> It seems the SKS keyserver pool is having some problem:
>> https://sks-keyservers.net/status/
>
>> The server is temporarily unable to service your request due to
>> maintenance downtime or capacity problems. Please try again later.
>
> Hmm, there does seem to be something up with the pool. On
> the other hand:
>
>> $ gpg --keyserver hkp://18.191.65.131 --recv-keys 7048B74B4C1B39E4
>
> This command with this specific server doesn't work for me
> (fails the same way with the "no valid user IDs" message),
> and using keyserver.ubuntu.com (which seems otherwise fine)
> also fails that way...

I'm not sure what else to do. I have submitted it to all of those key
servers through GPG and through the web interface. I never see an
error, but it doesn't show up under the web search.

Can you import it manually? The armour export is below:

-----BEGIN PGP PUBLIC KEY BLOCK-----
Version: GnuPG v2

mJMEWjNEzBMFK4EEACMEIwQAqL2RYVgUJ4UWEJbRAONWJmYGDBfl659Y5FRWfjYu
fBMZrj9DQarDC/P+QLOrBuwTmrBxXfg+/erVQKwYWDdnJG8AJ2m8Rli3wpYrxl/i
XqvEfKJmh6a1ZUiBZ7Ldnr0eNGzhVUWSyrAU+ImGSOutHUS8ytH3ZOeDOz2lj2kA
j6XYC+W0KUFsaXN0YWlyIEZyYW5jaXMgPGFsaXN0YWlyQGFsaXN0YWlyMjMubWU+
iNwEExMKAEECGwMFCQlmAYAFCwkIBwIGFQgJCgsCBBYCAwECHgECF4AWIQQp4Fkn
Y7HajIOZdf7kjjvCwSPtkwUCWjNE/AIZAQAKCRDkjjvCwSPtkyK6AgkBHJA7++aK
aeqvupdIPM87Yo2C7h+jsGVgTdr2N5uKS93xNOyn8rkAbGJV6GQXqjuEZgp1Ukvi
7M4o0Xk6XumOri8CB2T+v1CJedxNnNSE6rCdlaqJOxEKHA9oX8btksgpozRCbIMc
MZUMHadTc1GMMyoKg84hmLbk1vHtne4WQb3x6e/aiQEzBBMBCgAdFiEE867fg8U6
1eISTHkpuQvHq+fEHmUFAlszyGsACgkQuQvHq+fEHmVpQwf/ZEL7ww59KB7xPb5N
YuPVaFNZ2VsFPsaX3IZGi82Rgn7c2ZXcvQvv6V5nfn4zwK8m2MnTENBc4U+VJ+WT
/oump7npWaooJxTE8M9YE1pR8SaXdvPTzDCDjDVk52fX6/p/IFcjQnAoeKD3W5iL
KvS6i5yynEv1Onl7E5HFte72kmUhE4NhDaS0w6wataS75xdJapL+Ehh7dV1V9INJ
KqsIZr3KO+uHqgqhY1k6eT8LKZl4o2GYkNGQLvzRRuAXicICexKNZHKyrPcP3fZY
WCYtgE5BjckyW2sjdozg9q9no6DFde/p4Yz6JC5TJSpNBx9CSwqXOkjMNMujLRX+
mmJif7QnQWxpc3RhaXIgRnJhbmNpcyA8YWxpc3RhaXIyM0BnbWFpbC5jb20+iNoE
ExMKAD4WIQQp4FknY7HajIOZdf7kjjvCwSPtkwUCWjNE6AIbAwUJCWYBgAULCQgH
AgYVCAkKCwIEFgIDAQIeAQIXgAAKCRDkjjvCwSPtkxtHAgkBqlNesB/2Wr/j0Cd4
bhjwnpdWO5BGsKuLCBlnEgts6BEh5z5w7OEmgCYoEHTro6Q119D1hjmG5sLUn5AR
+SeVQ/8CCQGNuK/oIFS6MIXm66vrC1QwPyS5pdeXyZXKLK7sue515T86huQ0wdae
dt+UubuhLFNuP8MOZHWm5rum1R9X65TkTokBMwQTAQoAHRYhBPOu34PFOtXiEkx5
KbkLx6vnxB5lBQJbM8inAAoJELkLx6vnxB5lptQH+wUiSrZcrH2+n7Qlqe2e5u/s
8WWPS4+i8cxtZ6gpchUyTlaKRowFs+s6tAedwl5+gDZiQCxTwIP6fBxZeIC+Fen6
3zpzaE/EnxsqIAAa/zO30TIAHRqFp++m1DeZbarIho41ZY3A9X96UgN6jqj4zhVK
UTkkIFBye/MpYFB7xoMPuU90MgAtOPif4/vejXb3oYbllDXaomjfInqPnCiZc/1b
ApeQrIIlTVXrgExDVGQpHNQEHROtqjjwkhbKSPBwQ//rVPdiu61icJgcL8MVQfvP
IP5Vidi/X88xmlyWm+dCeTv62wRl9bCa4NQo3yL6M0uyaSS0j84ebVXHKTmxCyi5
AQ0EWjNF3wEIAMlri8jeUQabINXnrQmCAZMRTwJK/yqkN0mr7IJYLl77oTJm3ozO
dqMNCfidhH7XWb6mLRvpALffDQ3Wx1O7Q0zBe4M2SG2vGnO/y8O2FnXyKTDNJsD3
S2JA0l7UT9dNQFymcf73bXsECkz40d8xZS/QhO6fcynMwtkzITq3QDE3f5mk4FbH
1gYIftRRSzaO8cxbRuRroTs4+t7GgoWqVDpzr0ohoNqnFLqB5WHStH4ONhnLCYmk
L7eYTW97CvK5UqrZow2mzFCv+U87Sel6tcAGzF3NxB0+7aEiaJpYoBE1YjOjdOY7
whT5JqYKn7jScDuMBSkyvBuTKM3PsdJsqHEAEQEAAYi7BBgTCgAgFiEEKeBZJ2Ox
2oyDmXX+5I47wsEj7ZMFAlozRd8CGwwACgkQ5I47wsEj7ZNAhwIJAdfX/7+INmge
vMRtWRHoagkJgqxx9CfekHQceEgoDTIIY0HSFRH4KIkps8zVqMpaZp6f6bAWXk7t
SeSkTUXokzu5AgYhLTi/r0yoSpzMvnk770DLy4APwbs76cMt93BrcTUFtBlemYjf
oyylka9240l4re42UWmtN6XWjtt4LTiA1y8Pi7kBDQRaM0XkAQgAvyahH9xJ6X8m
Mce6tUNlHRoOuqLucyMTOIkRQmmUKSyCJNAAG+Wcrqda9k5G1R6Wz68joBY+LlwD
1J+UsA4mKrNrBrvrkj/vrjZ2pFCrzI6edYP8s492xc3Fty/5o3IyF9uyVoY+shgK
WC5tviJqyi0Isnbxygc/AyKPCa83eNz+ZWewHqvcxsdWzMAHWuTRqWZ0D/Nx26/G
dgxiLwgs7G2/f+iXe8MyWK1Shg++YJ3PNEZdSfAGJDUTgJXsIxi1o/Sd8VK3fT0N
7EO+U4cl3AIz2iN934ScIc3gODp6XrpxujkMbk4vPJ3N8cz9BNvml/Oj5btcufoZ
6gTVa8zbeQARAQABiQHyBBgTCgAgFiEEKeBZJ2Ox2oyDmXX+5I47wsEj7ZMFAloz
ReQCGwIBQAkQ5I47wsEj7ZPAdCAEGQEIAB0WIQQQDi9/5Hq6UCT/G1twSLdLTBs5
5AUCWjNF5AAKCRBwSLdLTBs55ANNCACDuAUcxBSLwCxRctsfMksCCUUmOAV9UK6Z
HmiqhWOBBl/1aw3mEEPsPucJ2rvdd0g4ntmka8J8rJVzRsJHv7z4eqAqET8rxFTv
4LSbckpBbSz1qHXklG1o0UVlIwVwVf6Wrs3aADy0XBGXqungR8Un5YpOmOJ7OvKq
fyJv/YgjUYaOtiPe0Re6J6QEqI+FC2e9lq4lOzA3Kwq09PSMbUL/gR7NGlQKgrQ2
6b71hz2+aOZGCygG4RZUON6mUb0k/Extj7h4NIXyTXXBDwNnR2qVWriDLVewQ8EO
yn/KXIoneR/D9nJHOIEmx9q8OYmc2TpxgQI8rz7uvjvuaw4XtH41ul4CCQFnkD5m
Qq4yP9xZgFiXYWFWdttV+8Kqlx2hH+hQFHmGFyNvwfty9JSegyu8iZ8gsKTy51he
2HqjVzYiImBrqa6i0QIJAY9e64iH+3PmjOYGsL5Hr5QSm0oyJG+/7KMRfvCSg/Qp
FmfzHamkd0ublxjF9ROxGdFwpRiNSOZ8XRd2YrCzZg/kuQENBFozRewBCACy2ayw
QK5cC6FO6CQdh7HhMJMLvT7QLerZ5FQnCfh1OG6wsMgQJbVYdr7La3tap4vNkhe6
jIPDko/ps0k6AhK8mYnP5bXumpzLHAzs3xYYHYmQ3GWDSQxX0ajbgAOSdLJF8vNM
NZBzm3AjPokX2/r0L8bMRSJ5a2QGXuy2ThrimLeojbYlTw6zajyFSLhHwkmiUCIh
uqRxe9UjLeVTq4Ejmm4NwvTA6cwRnpyndv05rkM5sDyNd9b4K5Y3eSZ2Yk8FBPPA
pWhPa0Oq8vjOu4oqacOBgY5cwvTCpNwMKYBFOmYhrZ8b6swk0fa/xK/C9zXvF69r
O+EmfRjJr6mk9nO5ABEBAAGIuwQYEwoAIBYhBCngWSdjsdqMg5l1/uSOO8LBI+2T
BQJaM0XsAhsgAAoJEOSOO8LBI+2TanQCCKi9gcTCpHtgtJOimUuTsthuH/K7f/M2
ZFeNgIm0k6HfKjgDCZMbK6evpuLuTrdeekyT1W0MLJIWmh0j3eJz31kZAgkBDOBs
Ezo6jhKug5aPbQ71GAy8tcKK783Ye2Ei0UCgTXGNdNZoPiYdhO7IX/QmNdMCtQ9R
zafpeVkcoSpABQrI2UQ=
=xMq1
-----END PGP PUBLIC KEY BLOCK-----

Alistair

>
> thanks
> -- PMM

Re: [Qemu-devel] [PULL 0/7] riscv-pull queue

[Peter Maydell]

On 29 June 2018 at 15:13, Alistair Francis <alistair23@gmail.com> wrote:
> Can you import it manually? The armour export is below:

Aha. I tried that, which didn't work either, which prompted
me to try --verbose, which says:

e104462:xenial:qemu-for-merges$ gpg --verbose --import /tmp/alistair.gpg
gpg: armour header: Version: GnuPG v2
gpg: can't handle public key algorithm 19
gpg: pub     0E/0xE48E3BC2C123ED93 2017-12-15  Alistair Francis
<alistair@alistair23.me>
gpg: key 0xE48E3BC2C123ED93: unsupported public key algorithm on user
ID "Alistair Francis <alistair@alistair23.me>"
gpg: key 0xE48E3BC2C123ED93: unsupported public key algorithm on user
ID "Alistair Francis <alistair23@gmail.com>"
gpg: key 0xE48E3BC2C123ED93: unsupported public key algorithm
gpg: key 0xE48E3BC2C123ED93: unsupported public key algorithm
gpg: key 0xE48E3BC2C123ED93: unsupported public key algorithm
gpg: key 0xE48E3BC2C123ED93: skipped user ID "Alistair Francis
<alistair@alistair23.me>"
gpg: key 0xE48E3BC2C123ED93: skipped user ID "Alistair Francis
<alistair23@gmail.com>"
gpg: key 0xE48E3BC2C123ED93: skipped subkey
gpg: key 0xE48E3BC2C123ED93: skipped subkey
gpg: key 0xE48E3BC2C123ED93: skipped subkey
gpg: key 0xE48E3BC2C123ED93: no valid user IDs
gpg: this may be caused by a missing self-signature
gpg: Total number processed: 1
gpg:           w/o user IDs: 1

So the problem is that your key is using some algorithm
that's too newfangled for my gpg to cope with...

thanks
-- PMM

Re: [Qemu-devel] [PULL 0/7] riscv-pull queue

[Alistair Francis]

On Fri, Jun 29, 2018 at 7:21 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 29 June 2018 at 15:13, Alistair Francis <alistair23@gmail.com> wrote:
>> Can you import it manually? The armour export is below:
>
> Aha. I tried that, which didn't work either, which prompted
> me to try --verbose, which says:
>
> e104462:xenial:qemu-for-merges$ gpg --verbose --import /tmp/alistair.gpg
> gpg: armour header: Version: GnuPG v2
> gpg: can't handle public key algorithm 19
> gpg: pub     0E/0xE48E3BC2C123ED93 2017-12-15  Alistair Francis
> <alistair@alistair23.me>
> gpg: key 0xE48E3BC2C123ED93: unsupported public key algorithm on user
> ID "Alistair Francis <alistair@alistair23.me>"
> gpg: key 0xE48E3BC2C123ED93: unsupported public key algorithm on user
> ID "Alistair Francis <alistair23@gmail.com>"
> gpg: key 0xE48E3BC2C123ED93: unsupported public key algorithm
> gpg: key 0xE48E3BC2C123ED93: unsupported public key algorithm
> gpg: key 0xE48E3BC2C123ED93: unsupported public key algorithm
> gpg: key 0xE48E3BC2C123ED93: skipped user ID "Alistair Francis
> <alistair@alistair23.me>"
> gpg: key 0xE48E3BC2C123ED93: skipped user ID "Alistair Francis
> <alistair23@gmail.com>"
> gpg: key 0xE48E3BC2C123ED93: skipped subkey
> gpg: key 0xE48E3BC2C123ED93: skipped subkey
> gpg: key 0xE48E3BC2C123ED93: skipped subkey
> gpg: key 0xE48E3BC2C123ED93: no valid user IDs
> gpg: this may be caused by a missing self-signature
> gpg: Total number processed: 1
> gpg:           w/o user IDs: 1
>
> So the problem is that your key is using some algorithm
> that's too newfangled for my gpg to cope with...

Hmm... I do use gpg2, but it's just an RSA2048 key.

Is it possible to update your GPG?

Otherwise I can try generating a new key just for QEMU PRs.

Alistair

>
> thanks
> -- PMM

Re: [Qemu-devel] [PULL 0/7] riscv-pull queue

[Philippe Mathieu-Daudé]

On 06/29/2018 11:21 AM, Peter Maydell wrote:
> On 29 June 2018 at 15:13, Alistair Francis <alistair23@gmail.com> wrote:
>> Can you import it manually? The armour export is below:
> 
> Aha. I tried that, which didn't work either, which prompted
> me to try --verbose, which says:
> 
> e104462:xenial:qemu-for-merges$ gpg --verbose --import /tmp/alistair.gpg
> gpg: armour header: Version: GnuPG v2
> gpg: can't handle public key algorithm 19
> gpg: pub     0E/0xE48E3BC2C123ED93 2017-12-15  Alistair Francis
> <alistair@alistair23.me>
> gpg: key 0xE48E3BC2C123ED93: unsupported public key algorithm on user
> ID "Alistair Francis <alistair@alistair23.me>"
> gpg: key 0xE48E3BC2C123ED93: unsupported public key algorithm on user
> ID "Alistair Francis <alistair23@gmail.com>"
> gpg: key 0xE48E3BC2C123ED93: unsupported public key algorithm
> gpg: key 0xE48E3BC2C123ED93: unsupported public key algorithm
> gpg: key 0xE48E3BC2C123ED93: unsupported public key algorithm
> gpg: key 0xE48E3BC2C123ED93: skipped user ID "Alistair Francis
> <alistair@alistair23.me>"
> gpg: key 0xE48E3BC2C123ED93: skipped user ID "Alistair Francis
> <alistair23@gmail.com>"
> gpg: key 0xE48E3BC2C123ED93: skipped subkey
> gpg: key 0xE48E3BC2C123ED93: skipped subkey
> gpg: key 0xE48E3BC2C123ED93: skipped subkey
> gpg: key 0xE48E3BC2C123ED93: no valid user IDs
> gpg: this may be caused by a missing self-signature
> gpg: Total number processed: 1
> gpg:           w/o user IDs: 1
> 
> So the problem is that your key is using some algorithm
> that's too newfangled for my gpg to cope with...

Oh indeed, this is a ECDH NISTP-521 public key!

Re: [Qemu-devel] [PULL 0/7] riscv-pull queue

[Daniel P. Berrangé]

On Fri, Jun 29, 2018 at 03:21:08PM +0100, Peter Maydell wrote:
> On 29 June 2018 at 15:13, Alistair Francis <alistair23@gmail.com> wrote:
> > Can you import it manually? The armour export is below:
> 
> Aha. I tried that, which didn't work either, which prompted
> me to try --verbose, which says:
> 
> e104462:xenial:qemu-for-merges$ gpg --verbose --import /tmp/alistair.gpg
> gpg: armour header: Version: GnuPG v2
> gpg: can't handle public key algorithm 19


This is an ECC algorithm, and only supported by gpg2 tool not gpg AFAICT.


Regards,
Daniel
-- 
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Re: [Qemu-devel] [PULL 0/7] riscv-pull queue

[Peter Maydell]

On 29 June 2018 at 15:27, Alistair Francis <alistair23@gmail.com> wrote:
> On Fri, Jun 29, 2018 at 7:21 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
>> So the problem is that your key is using some algorithm
>> that's too newfangled for my gpg to cope with...
>
> Hmm... I do use gpg2, but it's just an RSA2048 key.

Philippe says it's ECDH NISTP-521...

> Is it possible to update your GPG?

I don't believe any gpg(1) supports that algorithm.
I'm not really keen on moving to gpg2 because I hear bad
things about it...

thanks
-- PMM

Re: [Qemu-devel] [PULL 0/7] riscv-pull queue

[Alistair Francis]

On Fri, Jun 29, 2018 at 7:49 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 29 June 2018 at 15:27, Alistair Francis <alistair23@gmail.com> wrote:
>> On Fri, Jun 29, 2018 at 7:21 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
>>> So the problem is that your key is using some algorithm
>>> that's too newfangled for my gpg to cope with...
>>
>> Hmm... I do use gpg2, but it's just an RSA2048 key.
>
> Philippe says it's ECDH NISTP-521...
>
>> Is it possible to update your GPG?
>
> I don't believe any gpg(1) supports that algorithm.
> I'm not really keen on moving to gpg2 because I hear bad
> things about it...

Ok, I'll generate a new non-ECC key today and send a new PR.

Alistair

>
> thanks
> -- PMM