From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org, mjc@sifive.com
Cc: f4bug@amsat.org, alistair23@gmail.com,
Alistair Francis <alistair.francis@wdc.com>
Subject: [Qemu-devel] [PULL v2 6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/
Date: Fri, 29 Jun 2018 10:22:14 -0700 [thread overview]
Message-ID: <20180629172215.29475-7-alistair.francis@wdc.com> (raw)
In-Reply-To: <20180629172215.29475-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
---
hw/riscv/sifive_u.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index f71527eaff..46459cd368 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -194,7 +194,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(cells);
g_free(nodename);
- nodename = g_strdup_printf("/uart@%lx",
+ nodename = g_strdup_printf("/soc/uart@%lx",
(long)memmap[SIFIVE_U_UART0].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
--
2.17.1
next prev parent reply other threads:[~2018-06-29 17:22 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-29 17:22 [Qemu-devel] [PULL v2 0/7] riscv-pull queue Alistair Francis
2018-06-29 17:22 ` [Qemu-devel] [PULL v2 1/7] hw/riscv/sifive_u: Create a SiFive U SoC object Alistair Francis
2018-06-29 17:22 ` [Qemu-devel] [PULL v2 2/7] hw/riscv/sifive_e: Create a SiFive E " Alistair Francis
2018-06-29 17:22 ` [Qemu-devel] [PULL v2 3/7] hw/riscv/sifive_plic: Use gpios instead of irqs Alistair Francis
2018-06-29 17:22 ` [Qemu-devel] [PULL v2 4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus Alistair Francis
2018-06-29 17:22 ` [Qemu-devel] [PULL v2 5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts Alistair Francis
2018-06-29 17:22 ` Alistair Francis [this message]
2018-06-29 17:22 ` [Qemu-devel] [PULL v2 7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device Alistair Francis
2018-06-29 18:05 ` [Qemu-devel] [PULL v2 0/7] riscv-pull queue Philippe Mathieu-Daudé
2018-06-30 12:53 ` Peter Maydell
2018-07-03 15:57 ` Alistair Francis
2018-07-02 6:44 ` no-reply
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