From: Stafford Horne <shorne@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Development <qemu-devel@nongnu.org>,
Richard Henderson <richard.henderson@linaro.org>,
Stafford Horne <shorne@gmail.com>
Subject: [Qemu-devel] [PULL 05/25] target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB
Date: Mon, 2 Jul 2018 22:57:46 +0900 [thread overview]
Message-ID: <20180702135806.7087-6-shorne@gmail.com> (raw)
In-Reply-To: <20180702135806.7087-1-shorne@gmail.com>
From: Richard Henderson <richard.henderson@linaro.org>
No need to use the interrupt mechanisms when we can
simply exit the tb directly.
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/interrupt_helper.c | 3 +--
target/openrisc/translate.c | 6 +++---
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/target/openrisc/interrupt_helper.c b/target/openrisc/interrupt_helper.c
index 56620e0571..b865738f8b 100644
--- a/target/openrisc/interrupt_helper.c
+++ b/target/openrisc/interrupt_helper.c
@@ -26,7 +26,6 @@
void HELPER(rfe)(CPUOpenRISCState *env)
{
OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
#ifndef CONFIG_USER_ONLY
int need_flush_tlb = (cpu->env.sr & (SR_SM | SR_IME | SR_DME)) ^
(cpu->env.esr & (SR_SM | SR_IME | SR_DME));
@@ -53,8 +52,8 @@ void HELPER(rfe)(CPUOpenRISCState *env)
}
if (need_flush_tlb) {
+ CPUState *cs = CPU(cpu);
tlb_flush(cs);
}
#endif
- cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
}
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index f5af515979..43bdf378eb 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -37,6 +37,7 @@
#include "exec/log.h"
/* is_jmp field values */
+#define DISAS_EXIT DISAS_TARGET_0 /* force exit to main loop */
#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
typedef struct DisasContext {
@@ -1133,7 +1134,7 @@ static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a, uint32_t insn)
gen_illegal_exception(dc);
} else {
gen_helper_rfe(cpu_env);
- dc->base.is_jmp = DISAS_UPDATE;
+ dc->base.is_jmp = DISAS_EXIT;
}
#endif
return true;
@@ -1353,8 +1354,7 @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
case DISAS_NORETURN:
break;
case DISAS_UPDATE:
- /* indicate that the hash table must be used
- to find the next TB */
+ case DISAS_EXIT:
tcg_gen_exit_tb(NULL, 0);
break;
default:
--
2.17.0
next prev parent reply other threads:[~2018-07-02 13:58 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-02 13:57 [Qemu-devel] [PULL 00/25] OpenRISC updates for 3.0 Stafford Horne
2018-07-02 13:57 ` [Qemu-devel] [PULL 01/25] target/openrisc: Fix mtspr shadow gprs Stafford Horne
2018-07-02 13:57 ` [Qemu-devel] [PULL 02/25] target/openrisc: Add print_insn_or1k Stafford Horne
2018-07-02 13:57 ` [Qemu-devel] [PULL 03/25] target/openrisc: Log interrupts Stafford Horne
2018-07-02 13:57 ` [Qemu-devel] [PULL 04/25] target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP Stafford Horne
2018-07-02 13:57 ` Stafford Horne [this message]
2018-07-02 13:57 ` [Qemu-devel] [PULL 06/25] target/openrisc: Fix singlestep_enabled Stafford Horne
2018-07-02 13:57 ` [Qemu-devel] [PULL 07/25] target/openrisc: Link more translation blocks Stafford Horne
2018-07-02 13:57 ` [Qemu-devel] [PULL 09/25] target/openrisc: Exit the TB after l.mtspr Stafford Horne
2018-07-02 13:57 ` [Qemu-devel] [PULL 10/25] target/openrisc: Form the spr index from tcg Stafford Horne
2018-07-02 13:57 ` [Qemu-devel] [PULL 11/25] target/openrisc: Merge tlb allocation into CPUOpenRISCState Stafford Horne
2018-07-02 13:57 ` [Qemu-devel] [PULL 12/25] target/openrisc: Remove indirect function calls for mmu Stafford Horne
2018-07-02 13:57 ` [Qemu-devel] [PULL 13/25] target/openrisc: Merge mmu_helper.c into mmu.c Stafford Horne
2018-07-02 13:57 ` [Qemu-devel] [PULL 14/25] target/openrisc: Reduce tlb to a single dimension Stafford Horne
2018-07-02 13:57 ` [Qemu-devel] [PULL 15/25] target/openrisc: Fix tlb flushing in mtspr Stafford Horne
2018-07-02 13:57 ` [Qemu-devel] [PULL 16/25] target/openrisc: Fix cpu_mmu_index Stafford Horne
2018-07-02 13:57 ` [Qemu-devel] [PULL 17/25] target/openrisc: Use identical sizes for ITLB and DTLB Stafford Horne
2018-07-02 13:57 ` [Qemu-devel] [PULL 18/25] target/openrisc: Stub out handle_mmu_fault for softmmu Stafford Horne
2018-07-02 13:58 ` [Qemu-devel] [PULL 19/25] target/openrisc: Increase the TLB size Stafford Horne
2018-07-02 13:58 ` [Qemu-devel] [PULL 20/25] target/openrisc: Reorg tlb lookup Stafford Horne
2018-07-02 13:58 ` [Qemu-devel] [PULL 21/25] target/openrisc: Add support in scripts/qemu-binfmt-conf.sh Stafford Horne
2018-07-02 13:58 ` [Qemu-devel] [PULL 22/25] linux-user: Implement signals for openrisc Stafford Horne
2018-07-02 13:58 ` [Qemu-devel] [PULL 23/25] linux-user: Fix struct sigaltstack " Stafford Horne
2018-07-02 13:58 ` [Qemu-devel] [PULL 24/25] target/openrisc: Fix delay slot exception flag to match spec Stafford Horne
2018-07-02 13:58 ` [Qemu-devel] [PULL 25/25] target/openrisc: Fix writes to interrupt mask register Stafford Horne
2018-07-02 14:47 ` [Qemu-devel] [PULL 00/25] OpenRISC updates for 3.0 Stafford Horne
2018-07-02 15:34 ` Alex Bennée
2018-07-02 23:55 ` Stafford Horne
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