From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48491) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fa0TV-0003pF-D1 for qemu-devel@nongnu.org; Mon, 02 Jul 2018 11:10:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fa0TS-0007h0-Ux for qemu-devel@nongnu.org; Mon, 02 Jul 2018 11:10:45 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:44243) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fa0TS-0007fw-7b for qemu-devel@nongnu.org; Mon, 02 Jul 2018 11:10:42 -0400 Received: by mail-pf0-x241.google.com with SMTP id j3-v6so7649652pfh.11 for ; Mon, 02 Jul 2018 08:10:41 -0700 (PDT) From: Stafford Horne Date: Tue, 3 Jul 2018 00:09:59 +0900 Message-Id: <20180702151023.24532-2-shorne@gmail.com> In-Reply-To: <20180702151023.24532-1-shorne@gmail.com> References: <20180702151023.24532-1-shorne@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL v2 01/25] target/openrisc: Fix mtspr shadow gprs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: QEMU Development , Richard Henderson , Stafford Horne From: Richard Henderson Missing break when this feature was added in 89e71e873d ("target/openrisc: implement shadow registers"). This was causing strange issues as we get writes into the translation block jump cache and other bits of state. Fixes: 89e71e873d ("target/openrisc: implement shadow registers") Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Signed-off-by: Stafford Horne --- target/openrisc/sys_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index b284064381..2f337363ec 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -98,6 +98,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ idx = (spr - 1024); env->shadow_gpr[idx / 32][idx % 32] = rb; + break; case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); -- 2.17.0