From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38418) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fa1Ku-0004eu-8P for qemu-devel@nongnu.org; Mon, 02 Jul 2018 12:05:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fa1Kt-0005QP-Dj for qemu-devel@nongnu.org; Mon, 02 Jul 2018 12:05:56 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:37146) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fa1Kt-0005Pj-8J for qemu-devel@nongnu.org; Mon, 02 Jul 2018 12:05:55 -0400 Received: by mail-pg0-x242.google.com with SMTP id n15-v6so4107346pgv.4 for ; Mon, 02 Jul 2018 09:05:55 -0700 (PDT) From: Richard Henderson Date: Mon, 2 Jul 2018 09:05:43 -0700 Message-Id: <20180702160546.31969-4-richard.henderson@linaro.org> In-Reply-To: <20180702160546.31969-1-richard.henderson@linaro.org> References: <20180702160546.31969-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PULL 3/6] accel/tcg: Correct "is this a TLB miss" check in get_page_addr_code() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org From: Peter Maydell In commit 71b9a45330fe220d1 we changed the condition we use to determine whether we need to refill the TLB in get_page_addr_code() to if (unlikely(env->tlb_table[mmu_idx][index].addr_code != (addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)))) { This isn't the right check (it will falsely fail if the input addr happens to have the low bit corresponding to TLB_INVALID_MASK set, for instance). Replace it with a use of the new tlb_hit() function, which is the correct test. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell Message-Id: <20180629162122.19376-3-peter.maydell@linaro.org> Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index adb711963b..3ae1198c24 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -957,8 +957,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); mmu_idx = cpu_mmu_index(env, true); - if (unlikely(env->tlb_table[mmu_idx][index].addr_code != - (addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)))) { + if (unlikely(!tlb_hit(env->tlb_table[mmu_idx][index].addr_code, addr))) { if (!VICTIM_TLB_HIT(addr_read, addr)) { tlb_fill(ENV_GET_CPU(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0); } -- 2.17.1