From: Eduardo Habkost <ehabkost@redhat.com>
To: Robert Hoo <robert.hu@linux.intel.com>
Cc: qemu-devel@nongnu.org, pbonzini@redhat.com, rth@twiddle.net
Subject: Re: [Qemu-devel] [PATCH v2 2/5] i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR
Date: Tue, 3 Jul 2018 08:00:07 -0300 [thread overview]
Message-ID: <20180703110007.GL7451@localhost.localdomain> (raw)
In-Reply-To: <1530603313.22880.36.camel@linux.intel.com>
On Tue, Jul 03, 2018 at 03:35:13PM +0800, Robert Hoo wrote:
> On Thu, 2018-06-28 at 15:28 -0300, Eduardo Habkost wrote:
> > On Wed, Jun 27, 2018 at 07:27:21PM +0800, Robert Hoo wrote:
> > > Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as
> > > SPEC_CTRL.
> > >
> > > Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
> >
> > Based on kernel commit 1eaafe91, it looks like we must always set
> > IA32_ARCH_CAPABILITIES.RSBA[bit 2] unless we're really sure the
> > VM will not be migrated to a vulnerable processor.
> >
> > Considering this, I'd like to make "+arch-capabilities" set
> > IA32_ARCH_CAPABILITIES.RSBA by default, unless RSBA is explicitly
> > disabled by management software.
> >
> Agree. But this seems beyond Icelake CPU model scope. How about I think
> about this carefully and compose another patch (set) for this?
This plan makes sense to me, as I don't want to make this
decision block IceLake from being in QEMU 3.0.
However, enabling CPUID_7_0_EDX_ARCH_CAPABILITIES in IceLake but
setting the MSR to 0 seems pointless.
I think we should add IceLake without
CPUID_7_0_EDX_ARCH_CAPABILITIES first, and later (after deciding
on a reasonable default value for MSR_IA32_ARCH_CAPABILITIES),
enable the CPUID bit on IceLake (hopefully in time for QEMU 3.0).
> And you'd like to set IA32_ARCH_CAPABILITIES.RSBA by default in qemu or
> kvm layer?
Probably we need to make this decision in QEMU. If KVM set RSBA
automatically on .get_msr_feature(), QEMU won't be able to
differentiate a host with RSBA set from a host with RSBA unset.
--
Eduardo
next prev parent reply other threads:[~2018-07-03 12:15 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-27 11:27 [Qemu-devel] [PATCH v2 0/5] Add Icelake CPU model Robert Hoo
2018-06-27 11:27 ` [Qemu-devel] [PATCH v2 1/5] i386: Add support for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES MSRs Robert Hoo
2018-06-27 17:03 ` Eduardo Habkost
2018-06-28 9:25 ` Robert Hoo
2018-06-28 13:56 ` Eduardo Habkost
2018-06-28 14:20 ` Paolo Bonzini
2018-07-03 8:48 ` Robert Hoo
2018-07-03 9:06 ` Paolo Bonzini
2018-07-03 11:06 ` Eduardo Habkost
2018-07-03 11:07 ` Robert Hoo
2018-07-03 13:38 ` Paolo Bonzini
2018-07-04 6:33 ` Robert Hoo
2018-07-04 9:40 ` Paolo Bonzini
2018-07-13 14:11 ` konrad.wilk
2018-07-13 14:44 ` Paolo Bonzini
2018-07-13 14:52 ` Konrad Rzeszutek Wilk
2018-07-14 0:02 ` Robert Hoo
2018-06-27 11:27 ` [Qemu-devel] [PATCH v2 2/5] i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR Robert Hoo
2018-06-28 18:28 ` Eduardo Habkost
2018-07-03 7:35 ` Robert Hoo
2018-07-03 11:00 ` Eduardo Habkost [this message]
2018-07-12 9:18 ` Robert Hoo
2018-07-12 15:47 ` Paolo Bonzini
2018-06-27 11:27 ` [Qemu-devel] [PATCH v2 3/5] i386: Add CPUID bit for PCONFIG Robert Hoo
2018-06-27 11:27 ` [Qemu-devel] [PATCH v2 4/5] i386: Add CPUID bit for WBNOINVD Robert Hoo
2018-06-27 11:27 ` [Qemu-devel] [PATCH v2 5/5] i386: Add new CPU model Icelake-{Server, Client} Robert Hoo
2018-07-02 2:31 ` [Qemu-devel] [PATCH v2 0/5] Add Icelake CPU model no-reply
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