From: Eduardo Habkost <ehabkost@redhat.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: Robert Hoo <robert.hu@linux.intel.com>,
qemu-devel@nongnu.org, wei.w.wang@intel.com
Subject: Re: [Qemu-devel] [PATCH v2 1/5] i386: Add support for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES MSRs
Date: Tue, 3 Jul 2018 08:06:17 -0300 [thread overview]
Message-ID: <20180703110617.GM7451@localhost.localdomain> (raw)
In-Reply-To: <b7c410af-ebc0-537c-84c4-588842fec111@redhat.com>
On Tue, Jul 03, 2018 at 11:06:00AM +0200, Paolo Bonzini wrote:
> On 03/07/2018 10:48, Robert Hoo wrote:
> >>
> >> However, I suggest adding it to the FeatureWord enum, since everything
> >> that handles FeatureWord applies to this new kind of MSR as well.
> >> Currently FeatureWord is only for CPUID leaves, but it doesn't have to
> >> be like that.
> >>
> > I think this will be changing struct FeatureWordInfo, which is designed
> > for cpuid enumerations. You must not want to do that. May I know more
> > details about your thought?
>
> The simplest way is to put CPUIDs first and MSRs second in FeatureWord.
> Then you can do
>
> FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
> FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
> + FEATURE_WORDS_NUM_CPUID,
> + FEATURE_WORDS_FIRST_MSR = FEATURE_WORDS_NUM_CPUID,
> + FEAT_MSR_ARCH_CAPABILITIES = FEATURE_WORDS_FIRST_MSR,
> FEATURE_WORDS,
> };
>
> #define FEATURE_WORDS_NUM_MSRS (FEATURE_WORDS - \
> FEATURE_WORDS_FIRST_MSR)
>
> Then the existing loops that use FeatureWordInfo can go up to
> FEATURE_WORDS_NUM_CPUID.
I assume we want to make some (or most) of the loops go up to
FEATURE_WORDS (e.g. make x86_cpu_get_supported_feature_word()
support MSRs too), otherwise it would be pointless to reuse the
same array.
I would be OK with both approaches, though. If the first version
doesn't use the `features[]` array and implements this with a
separate `msr_features[]` or `msr_arch_capabilities` field, it
would work for me (especially if this means we can get this
implemented in time for QEMU 3.0).
--
Eduardo
next prev parent reply other threads:[~2018-07-03 11:06 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-27 11:27 [Qemu-devel] [PATCH v2 0/5] Add Icelake CPU model Robert Hoo
2018-06-27 11:27 ` [Qemu-devel] [PATCH v2 1/5] i386: Add support for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES MSRs Robert Hoo
2018-06-27 17:03 ` Eduardo Habkost
2018-06-28 9:25 ` Robert Hoo
2018-06-28 13:56 ` Eduardo Habkost
2018-06-28 14:20 ` Paolo Bonzini
2018-07-03 8:48 ` Robert Hoo
2018-07-03 9:06 ` Paolo Bonzini
2018-07-03 11:06 ` Eduardo Habkost [this message]
2018-07-03 11:07 ` Robert Hoo
2018-07-03 13:38 ` Paolo Bonzini
2018-07-04 6:33 ` Robert Hoo
2018-07-04 9:40 ` Paolo Bonzini
2018-07-13 14:11 ` konrad.wilk
2018-07-13 14:44 ` Paolo Bonzini
2018-07-13 14:52 ` Konrad Rzeszutek Wilk
2018-07-14 0:02 ` Robert Hoo
2018-06-27 11:27 ` [Qemu-devel] [PATCH v2 2/5] i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR Robert Hoo
2018-06-28 18:28 ` Eduardo Habkost
2018-07-03 7:35 ` Robert Hoo
2018-07-03 11:00 ` Eduardo Habkost
2018-07-12 9:18 ` Robert Hoo
2018-07-12 15:47 ` Paolo Bonzini
2018-06-27 11:27 ` [Qemu-devel] [PATCH v2 3/5] i386: Add CPUID bit for PCONFIG Robert Hoo
2018-06-27 11:27 ` [Qemu-devel] [PATCH v2 4/5] i386: Add CPUID bit for WBNOINVD Robert Hoo
2018-06-27 11:27 ` [Qemu-devel] [PATCH v2 5/5] i386: Add new CPU model Icelake-{Server, Client} Robert Hoo
2018-07-02 2:31 ` [Qemu-devel] [PATCH v2 0/5] Add Icelake CPU model no-reply
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