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From: Julia Suvorova <jusual@mail.ru>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
	"Stefan Hajnoczi" <stefanha@redhat.com>,
	"Joel Stanley" <joel@jms.id.au>,
	"Jim Mussared" <jim@groklearning.com>,
	"Steffen Görtz" <mail@steffen-goertz.de>,
	"Julia Suvorova" <jusual@mail.ru>
Subject: [Qemu-devel] [RFC v3 2/2] tests: Add ARMv6-M reserved register test
Date: Fri,  6 Jul 2018 01:21:15 +0300	[thread overview]
Message-ID: <20180705222115.17013-3-jusual@mail.ru> (raw)
In-Reply-To: <20180705222115.17013-1-jusual@mail.ru>

Check that reserved SCS registers return 0 at read,
and writes are ignored.

Based-on: <20180627143815.1829-1-joel@jms.id.au>
Based-on: <20180630091343.14391-1-stefanha@redhat.com>

Signed-off-by: Julia Suvorova <jusual@mail.ru>
---
Test will work if Joel's patches will use ARMv6-M.

 tests/Makefile.include            |  2 ++
 tests/tcg/arm/test-reserved-reg.c | 60 +++++++++++++++++++++++++++++++
 2 files changed, 62 insertions(+)
 create mode 100644 tests/tcg/arm/test-reserved-reg.c

diff --git a/tests/Makefile.include b/tests/Makefile.include
index d323c42682..8ab0b0d15f 100644
--- a/tests/Makefile.include
+++ b/tests/Makefile.include
@@ -387,6 +387,7 @@ gcov-files-arm-y += hw/timer/arm_mptimer.c
 check-qtest-arm-y += tests/boot-serial-test$(EXESUF)
 check-qtest-arm-y += tests/sdhci-test$(EXESUF)
 check-qtest-arm-y += tests/hexloader-test$(EXESUF)
+check-qtest-arm-y += tests/tcg/arm/test-reserved-reg$(EXESUF)
 
 check-qtest-aarch64-y = tests/numa-test$(EXESUF)
 check-qtest-aarch64-y += tests/sdhci-test$(EXESUF)
@@ -771,6 +772,7 @@ tests/device-introspect-test$(EXESUF): tests/device-introspect-test.o
 tests/rtc-test$(EXESUF): tests/rtc-test.o
 tests/m48t59-test$(EXESUF): tests/m48t59-test.o
 tests/hexloader-test$(EXESUF): tests/hexloader-test.o
+tests/test-reserved-reg$(EXESUF): tests/tcg/arm/test-reserved-reg.o
 tests/endianness-test$(EXESUF): tests/endianness-test.o
 tests/spapr-phb-test$(EXESUF): tests/spapr-phb-test.o $(libqos-obj-y)
 tests/prom-env-test$(EXESUF): tests/prom-env-test.o $(libqos-obj-y)
diff --git a/tests/tcg/arm/test-reserved-reg.c b/tests/tcg/arm/test-reserved-reg.c
new file mode 100644
index 0000000000..97273ff24d
--- /dev/null
+++ b/tests/tcg/arm/test-reserved-reg.c
@@ -0,0 +1,60 @@
+/*
+ * Test ARMv6-M SCS reserved registers
+ *
+ * Copyright (c) 2018 Julia Suvorova <jusual@mail.ru>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2
+ * or later. See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "libqtest.h"
+
+static void test_reserved_reg(void)
+{
+    QTestState *s;
+    int i;
+    static const uint64_t reserved_reg[] = { 0xe000ed10, /* SCR */
+                                             0xe000ed18, /* SHPR1 */
+                                             0xe000ed28, /* CFSR */
+                                             0xe000ed2c, /* HFSR */
+                                             0xe000ed34, /* MMFAR */
+                                             0xe000ed38, /* BFAR */
+                                             0xe000ed3c, /* AFSR */
+                                             0xe000ed40, /* CPUID */
+                                             0xe000ed88, /* CPACR */
+                                             0xe000ef00  /* STIR */ };
+    static const uint8_t mini_kernel[] = { 0x00, 0x00, 0x00, 0x00,
+                                           0x09, 0x00, 0x00, 0x00 };
+    ssize_t wlen, kernel_size = sizeof(mini_kernel);
+    int code_fd;
+    char codetmp[] = "/tmp/reserved-reg-test-XXXXXX";
+
+    code_fd = mkstemp(codetmp);
+    wlen = write(code_fd, mini_kernel, sizeof(mini_kernel));
+    g_assert(wlen == kernel_size);
+    close(code_fd);
+
+    s = qtest_startf("-kernel %s -M microbit -nographic", codetmp);
+
+    for (i = 0; i < ARRAY_SIZE(reserved_reg); i++) {
+        int res;
+        qtest_writel(s, reserved_reg[i], 1);
+        res = qtest_readl(s, reserved_reg[i]);
+        g_assert(!res);
+    }
+
+    qtest_quit(s);
+}
+
+int main(int argc, char **argv)
+{
+    int ret;
+
+    g_test_init(&argc, &argv, NULL);
+
+    qtest_add_func("tcg/arm/test-reserved-reg", test_reserved_reg);
+    ret = g_test_run();
+
+    return ret;
+}
-- 
2.17.1

  parent reply	other threads:[~2018-07-05 22:21 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-05 22:21 [Qemu-devel] [PATCH v3 0/2] nvic: Handle ARMv6-M SCS reserved registers Julia Suvorova
2018-07-05 22:21 ` [Qemu-devel] [PATCH v3 1/2] " Julia Suvorova
2018-07-06 15:05   ` Peter Maydell
2018-07-05 22:21 ` Julia Suvorova [this message]
2018-07-06 14:55   ` [Qemu-devel] [RFC v3 2/2] tests: Add ARMv6-M reserved register test Peter Maydell
2018-07-11 13:00     ` Stefan Hajnoczi

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