From: David Gibson <david@gibson.dropbear.id.au>
To: Sebastian Bauer <mail@sebastianbauer.info>
Cc: BALATON Zoltan <balaton@eik.bme.hu>,
Peter Maydell <peter.maydell@linaro.org>,
Alexander Graf <agraf@suse.de>, qemu-ppc <qemu-ppc@nongnu.org>,
QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH] sam460ex: Fix PCI interrupt connections
Date: Tue, 31 Jul 2018 16:06:17 +1000 [thread overview]
Message-ID: <20180731060617.GJ2708@umbus.fritz.box> (raw)
In-Reply-To: <52bff728ba683daa71e32be776a55ff0@sebastianbauer.info>
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On Tue, Jul 31, 2018 at 06:57:31AM +0200, Sebastian Bauer wrote:
> Am 2018-07-31 02:18, schrieb David Gibson:
> > > David, can you please drop this patch, we'll come up with a
> > > different fix.
> > Done. Should have looked at that patch a bit closer.
>
> I created a follow up patch, unfortunately, based on the previous patch, as
> I did not spot your mail earlier than now. Note that the previous patch was
> an improvement over the old behaviour and under normal conditions the
> difference was not visible (as the OS serves both interrupts in the same run
> and at least on AmigaOS the interrupt handling is deferred but IRQs are
> acked quickly; it is still not correct though). The old implementation was
> not correct at all, i.e., all interrupts were missed. So it was technical an
> improvement (and the easiest to come up without deep understanding QEMU) ;)
>
> Anyway, I don't know if that follow up patch is the right approach. But
> building the logical or gate seems also be very much code, especially as in
> pci.c the case of multiple irqs sources are seems to be already handled (if
> I understand that code correctly). The follow up patch most likely does not
> model the hardware correctly, but the behaviour should be the same. The
> logical or gate would model the hardware more closely.
Yeah, I think routing all the irqs to pin A should be ok for now.
AIUI it's not user or guest visible so we can fix it up later if we
get more information on the hardware. I believe there are a number of
other embedded boards that have a similar hack too, since they only
have a single PCI LSI line on the board-level PIC.
> Let me know if I should rebase to the state before my initial patch (I just
> looked and the previous patch was still not dropped) if you think that the
> change is fine.
I'd prefer a rebase onto the current state of my ppc-for-3.0 tree,
please.
> There is also the possibility to make the special (num-irqs == 1) the common
> case, as the Sam460ex platform is the only user of this bus so far (and
> probably stays the only one). I'm not sure if it is worth all the hassle.
> Also note that the entire ppc440_pcix.c source file seems to be created for
> the sam board. I have no idea why that mapping function based on slots was
> chosen in the first place so I kept it. I would also be fine to remove that,
> which would simplify things a lot.
>
> Let me know how to proceed.
>
> Bye
> Sebastian
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2018-07-31 6:17 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-30 4:39 [Qemu-devel] [PATCH] sam460ex: Fix PCI interrupt connections Sebastian Bauer
2018-07-30 4:49 ` David Gibson
2018-07-30 11:06 ` BALATON Zoltan
2018-07-30 12:04 ` Sebastian Bauer
2018-07-30 22:37 ` BALATON Zoltan
2018-07-30 23:00 ` Peter Maydell
2018-07-30 23:31 ` BALATON Zoltan
2018-07-31 0:18 ` David Gibson
2018-07-31 4:57 ` Sebastian Bauer
2018-07-31 6:06 ` David Gibson [this message]
2018-07-31 9:50 ` BALATON Zoltan
2018-07-31 10:32 ` Sebastian Bauer
2018-07-31 11:24 ` [Qemu-devel] [Qemu-ppc] " BALATON Zoltan
2018-07-30 22:47 ` [Qemu-devel] " Peter Maydell
2018-07-30 23:00 ` BALATON Zoltan
2018-07-30 23:15 ` Peter Maydell
2018-07-31 5:09 ` Sebastian Bauer
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