[Qemu-devel] [PATCH 0/2] target/ppc: Fixes for my fpu cleanups

[Qemu-devel] [PATCH 0/2] target/ppc: Fixes for my fpu cleanups

[Richard Henderson]

David, please squash these with the patches you already
have on your ppc-for-3.1 branch.

The first fixes fp division within the vector insns.
The second fixes some typos within the load/store converters
as reported by Mark Cave-Ayland.


r~


Richard Henderson (2):
  fixup! target/ppc: Honor fpscr_ze semantics and tidy fdiv
  fixup! target/ppc: Use non-arithmetic conversions for fp load/store

 target/ppc/fpu_helper.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

-- 
2.17.1

[Qemu-devel] [PATCH 1/2] fixup! target/ppc: Honor fpscr_ze semantics and tidy fdiv

[Richard Henderson]

---
 target/ppc/fpu_helper.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index cb82e6e842..faea64020b 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -1965,6 +1965,9 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)                           \
                 tp##_is_signaling_nan(xb.fld, &tstat)) {                      \
                 float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);    \
             }                                                                 \
+        }                                                                     \
+        if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) {   \
+            float_zero_divide_excp(env, GETPC());                             \
         }                                                                     \
                                                                               \
         if (r2sp) {                                                           \
@@ -2015,6 +2018,9 @@ void helper_xsdivqp(CPUPPCState *env, uint32_t opcode)
             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
         }
     }
+    if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) {
+        float_zero_divide_excp(env, GETPC());
+    }
 
     helper_compute_fprf_float128(env, xt.f128);
     putVSR(rD(opcode) + 32, &xt, env);
-- 
2.17.1

[Qemu-devel] [PATCH 2/2] fixup! target/ppc: Use non-arithmetic conversions for fp load/store

[Richard Henderson]

---
 target/ppc/fpu_helper.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index faea64020b..b9bb1b856e 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -61,7 +61,7 @@ uint64_t helper_todouble(uint32_t arg)
         /* Normalized operand, or Inf, or NaN.  */
         ret  = (uint64_t)extract32(arg, 30, 2) << 62;
         ret |= ((extract32(arg, 30, 1) ^ 1) * (uint64_t)7) << 59;
-        ret |= (uint64_t)extract32(arg, 0, 29) << 29;
+        ret |= (uint64_t)extract32(arg, 0, 30) << 29;
     } else {
         /* Zero or Denormalized operand.  */
         ret = (uint64_t)extract32(arg, 31, 1) << 63;
@@ -88,14 +88,14 @@ uint32_t helper_tosingle(uint64_t arg)
     if (likely(exp > 896)) {
         /* No denormalization required (includes Inf, NaN).  */
         ret  = extract64(arg, 62, 2) << 30;
-        ret |= extract64(arg, 29, 29);
+        ret |= extract64(arg, 29, 30);
     } else {
         /* Zero or Denormal result.  If the exponent is in bounds for
          * a single-precision denormal result, extract the proper bits.
          * If the input is not zero, and the exponent is out of bounds,
          * then the result is undefined; this underflows to zero.
          */
-        ret = extract64(arg, 63, 1) << 63;
+        ret = extract64(arg, 63, 1) << 31;
         if (unlikely(exp >= 874)) {
             /* Denormal result.  */
             ret |= ((1ULL << 52) | extract64(arg, 0, 52)) >> (896 + 30 - exp);
-- 
2.17.1

Re: [Qemu-devel] [PATCH 0/2] target/ppc: Fixes for my fpu cleanups

[David Gibson]

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On Sun, Aug 05, 2018 at 06:27:21PM -0700, Richard Henderson wrote:
> David, please squash these with the patches you already
> have on your ppc-for-3.1 branch.
> 
> The first fixes fp division within the vector insns.
> The second fixes some typos within the load/store converters
> as reported by Mark Cave-Ayland.

Done, thanks.

> 
> 
> r~
> 
> 
> Richard Henderson (2):
>   fixup! target/ppc: Honor fpscr_ze semantics and tidy fdiv
>   fixup! target/ppc: Use non-arithmetic conversions for fp load/store
> 
>  target/ppc/fpu_helper.c | 12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)
> 

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [PATCH 0/2] target/ppc: Fixes for my fpu cleanups

[Mark Cave-Ayland]

On 06/08/18 02:27, Richard Henderson wrote:

> David, please squash these with the patches you already
> have on your ppc-for-3.1 branch.
> 
> The first fixes fp division within the vector insns.
> The second fixes some typos within the load/store converters
> as reported by Mark Cave-Ayland.

I've just given David's updated ppc-for-3.1 branch a spin with my 
OpenBIOS test images and it looks like MacOS 9 is working again, and no 
obvious regressions spotted so far - thanks a lot!


ATB,

Mark.