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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org,
	alex.bennee@linaro.org
Subject: [Qemu-devel] [PATCH 02/20] target/arm: Set ID_AA64PFR0 bits for SVE for -cpu max
Date: Wed,  8 Aug 2018 21:21:48 -0700	[thread overview]
Message-ID: <20180809042206.15726-3-richard.henderson@linaro.org> (raw)
In-Reply-To: <20180809042206.15726-1-richard.henderson@linaro.org>

This it a hair out of spec in that we have and advertise, support
for fp16 in aarch64 mode, but do not have nor advertise the same
in aarch32 mode.  Rationale as commented.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu64.c | 21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 4d629bb99b..ae650b608e 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -282,15 +282,24 @@ static void aarch64_max_initfn(Object *obj)
         cpu->id_aa64isar1 = deposit64(cpu->id_aa64isar1, 16, 4, 1);
         cpu->id_isar5 = deposit32(cpu->id_isar5, 28, 4, 1);
 
-#ifdef CONFIG_USER_ONLY
-        /* We don't set these in system emulation mode for the moment,
-         * since we don't correctly set the ID registers to advertise them,
-         * and in some cases they're only available in AArch64 and not AArch32,
-         * whereas the architecture requires them to be present in both if
-         * present in either.
+        /* TODO: This is not yet implemented for AArch32, whereas the
+         * architecture requires a feature to be present in both if
+         * it is present in either.  However, it is required by SVE,
+         * so we don't want to leave it out of AArch64 state.
+         *
+         * Practically, the Linux kernel does not query the MVFR1 bit
+         * nor expose this as a HWCAP bit to AArch32 userland.  Thus
+         * userland, if it wanted to use fp16, would have to probe for
+         * support by executing an insn and checking for SIGILL.
+         * At which point it will get the correct answer: unsupported.
          */
         set_feature(&cpu->env, ARM_FEATURE_V8_FP16);
+        cpu->id_aa64pfr0 = deposit64(cpu->id_aa64pfr0, 20, 4, 1);
+
         set_feature(&cpu->env, ARM_FEATURE_SVE);
+        cpu->id_aa64pfr0 = deposit64(cpu->id_aa64pfr0, 32, 4, 1);
+
+#ifdef CONFIG_USER_ONLY
         /* For usermode -cpu max we can use a larger and more efficient DCZ
          * blocksize since we don't have to follow what the hardware does.
          */
-- 
2.17.1

  parent reply	other threads:[~2018-08-09  4:22 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-09  4:21 [Qemu-devel] [PATCH 00/20] target/arm: sve system mode patches Richard Henderson
2018-08-09  4:21 ` [Qemu-devel] [PATCH 01/20] target/arm: Set ISAR bits for -cpu max Richard Henderson
2018-08-09  4:21 ` Richard Henderson [this message]
2018-08-09  4:21 ` [Qemu-devel] [PATCH 03/20] target/arm: Define ID_AA64ZFR0_EL1 Richard Henderson
2018-08-17 15:50   ` Peter Maydell
2018-08-09  4:21 ` [Qemu-devel] [PATCH 04/20] target/arm: Adjust sve_exception_el Richard Henderson
2018-08-17 15:57   ` Peter Maydell
2018-08-09  4:21 ` [Qemu-devel] [PATCH 05/20] target/arm: Fix arm_cpu_data_is_big_endian for aa64 user-only Richard Henderson
2018-08-17 16:02   ` Peter Maydell
2018-08-17 16:47     ` Richard Henderson
2018-08-09  4:21 ` [Qemu-devel] [PATCH 06/20] target/arm: Fix arm_current_el for user-only Richard Henderson
2018-08-17 16:03   ` Peter Maydell
2018-08-17 16:51     ` Richard Henderson
2018-08-09  4:21 ` [Qemu-devel] [PATCH 07/20] target/arm: Fix is_a64 " Richard Henderson
2018-08-17 16:03   ` Peter Maydell
2018-08-17 16:10     ` Laurent Desnogues
2018-08-17 16:23       ` Peter Maydell
2018-08-09  4:21 ` [Qemu-devel] [PATCH 08/20] target/arm: Pass in current_el to fp and sve_exception_el Richard Henderson
2018-08-09 18:01   ` Alex Bennée
2018-08-09 18:50     ` Richard Henderson
2018-08-09  4:21 ` [Qemu-devel] [PATCH 09/20] target/arm: Handle SVE vector length changes in system mode Richard Henderson
2018-08-17 16:22   ` Peter Maydell
2018-08-25 19:41     ` Richard Henderson
2018-08-09  4:21 ` [Qemu-devel] [PATCH 10/20] target/arm: Adjust aarch64_cpu_dump_state for system mode SVE Richard Henderson
2018-08-17 16:35   ` Peter Maydell
2018-08-09  4:21 ` [Qemu-devel] [PATCH 11/20] target/arm: Clear unused predicate bits for LD1RQ Richard Henderson
2018-08-23 15:21   ` Peter Maydell
2018-08-23 15:37     ` Richard Henderson
2018-08-09  4:21 ` [Qemu-devel] [PATCH 12/20] target/arm: Rewrite helper_sve_ld1*_r using pages Richard Henderson
2018-08-10  9:13   ` Alex Bennée
2018-08-10 19:15     ` Richard Henderson
2018-08-23 16:01   ` Peter Maydell
2018-08-09  4:21 ` [Qemu-devel] [PATCH 13/20] target/arm: Rewrite helper_sve_ld[234]*_r Richard Henderson
2018-08-23 16:04   ` Peter Maydell
2018-08-09  4:22 ` [Qemu-devel] [PATCH 14/20] target/arm: Rewrite helper_sve_st[1234]*_r Richard Henderson
2018-08-23 16:06   ` Peter Maydell
2018-08-09  4:22 ` [Qemu-devel] [PATCH 15/20] target/arm: Split contiguous loads for endianness Richard Henderson
2018-08-11  5:40   ` Philippe Mathieu-Daudé
2018-08-09  4:22 ` [Qemu-devel] [PATCH 16/20] target/arm: Split contiguous stores " Richard Henderson
2018-08-11  5:41   ` Philippe Mathieu-Daudé
2018-08-09  4:22 ` [Qemu-devel] [PATCH 17/20] target/arm: Rewrite vector gather loads Richard Henderson
2018-08-23 16:08   ` Peter Maydell
2018-08-09  4:22 ` [Qemu-devel] [PATCH 18/20] target/arm: Rewrite vector gather stores Richard Henderson
2018-08-23 16:09   ` Peter Maydell
2018-08-09  4:22 ` [Qemu-devel] [PATCH 19/20] target/arm: Rewrite vector gather first-fault loads Richard Henderson
2018-08-23 16:10   ` Peter Maydell
2018-08-09  4:22 ` [Qemu-devel] [PATCH 20/20] target/arm: Pass TCGMemOpIdx to sve memory helpers Richard Henderson
2018-08-23 16:23   ` Peter Maydell
2018-08-09  5:48 ` [Qemu-devel] [PATCH 00/20] target/arm: sve system mode patches Laurent Desnogues
2018-08-18  9:15 ` no-reply
2018-08-18 10:01 ` no-reply

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