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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: patches@linaro.org
Subject: [Qemu-devel] [PATCH 10/16] hw/dma/pl080: Allow use as embedded-struct device
Date: Thu,  9 Aug 2018 14:01:09 +0100	[thread overview]
Message-ID: <20180809130115.28951-11-peter.maydell@linaro.org> (raw)
In-Reply-To: <20180809130115.28951-1-peter.maydell@linaro.org>

Create a new include file for the pl081's device struct,
type macros, etc, so that it can be instantiated using
the "embedded struct" coding style.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/dma/pl080.h | 62 ++++++++++++++++++++++++++++++++++++++++++
 hw/dma/pl080.c         | 34 ++---------------------
 MAINTAINERS            |  1 +
 3 files changed, 65 insertions(+), 32 deletions(-)
 create mode 100644 include/hw/dma/pl080.h

diff --git a/include/hw/dma/pl080.h b/include/hw/dma/pl080.h
new file mode 100644
index 00000000000..7deb46c8578
--- /dev/null
+++ b/include/hw/dma/pl080.h
@@ -0,0 +1,62 @@
+/*
+ * ARM PrimeCell PL080/PL081 DMA controller
+ *
+ * Copyright (c) 2006 CodeSourcery.
+ * Copyright (c) 2018 Linaro Limited
+ * Written by Paul Brook, Peter Maydell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or
+ * (at your option) any later version.
+ */
+
+/* This is a model of the Arm PrimeCell PL080/PL081 DMA controller:
+ * The PL080 TRM is:
+ * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0196g/DDI0196.pdf
+ * and the PL081 TRM is:
+ * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0218e/DDI0218.pdf
+ *
+ * QEMU interface:
+ * + sysbus IRQ: DMACINTR combined interrupt line
+ * + sysbus MMIO region 0: MemoryRegion for the device's registers
+ */
+
+#ifndef HW_DMA_PL080_H
+#define HW_DMA_PL080_H
+
+#include "hw/sysbus.h"
+
+#define PL080_MAX_CHANNELS 8
+
+typedef struct {
+    uint32_t src;
+    uint32_t dest;
+    uint32_t lli;
+    uint32_t ctrl;
+    uint32_t conf;
+} pl080_channel;
+
+#define TYPE_PL080 "pl080"
+#define TYPE_PL081 "pl081"
+#define PL080(obj) OBJECT_CHECK(PL080State, (obj), TYPE_PL080)
+
+typedef struct PL080State {
+    SysBusDevice parent_obj;
+
+    MemoryRegion iomem;
+    uint8_t tc_int;
+    uint8_t tc_mask;
+    uint8_t err_int;
+    uint8_t err_mask;
+    uint32_t conf;
+    uint32_t sync;
+    uint32_t req_single;
+    uint32_t req_burst;
+    pl080_channel chan[PL080_MAX_CHANNELS];
+    int nchannels;
+    /* Flag to avoid recursive DMA invocations.  */
+    int running;
+    qemu_irq irq;
+} PL080State;
+
+#endif
diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c
index 7724c93b8f2..0f79c2d8a6c 100644
--- a/hw/dma/pl080.c
+++ b/hw/dma/pl080.c
@@ -11,8 +11,8 @@
 #include "hw/sysbus.h"
 #include "exec/address-spaces.h"
 #include "qemu/log.h"
+#include "hw/dma/pl080.h"
 
-#define PL080_MAX_CHANNELS 8
 #define PL080_CONF_E    0x1
 #define PL080_CONF_M1   0x2
 #define PL080_CONF_M2   0x4
@@ -30,36 +30,6 @@
 #define PL080_CCTRL_D   0x02000000
 #define PL080_CCTRL_S   0x01000000
 
-typedef struct {
-    uint32_t src;
-    uint32_t dest;
-    uint32_t lli;
-    uint32_t ctrl;
-    uint32_t conf;
-} pl080_channel;
-
-#define TYPE_PL080 "pl080"
-#define PL080(obj) OBJECT_CHECK(PL080State, (obj), TYPE_PL080)
-
-typedef struct PL080State {
-    SysBusDevice parent_obj;
-
-    MemoryRegion iomem;
-    uint8_t tc_int;
-    uint8_t tc_mask;
-    uint8_t err_int;
-    uint8_t err_mask;
-    uint32_t conf;
-    uint32_t sync;
-    uint32_t req_single;
-    uint32_t req_burst;
-    pl080_channel chan[PL080_MAX_CHANNELS];
-    int nchannels;
-    /* Flag to avoid recursive DMA invocations.  */
-    int running;
-    qemu_irq irq;
-} PL080State;
-
 static const VMStateDescription vmstate_pl080_channel = {
     .name = "pl080_channel",
     .version_id = 1,
@@ -408,7 +378,7 @@ static const TypeInfo pl080_info = {
 };
 
 static const TypeInfo pl081_info = {
-    .name          = "pl081",
+    .name          = TYPE_PL081,
     .parent        = TYPE_PL080,
     .instance_init = pl081_init,
 };
diff --git a/MAINTAINERS b/MAINTAINERS
index 5d1a3645dd4..92ccca716c6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -444,6 +444,7 @@ F: hw/char/pl011.c
 F: include/hw/char/pl011.h
 F: hw/display/pl110*
 F: hw/dma/pl080.c
+F: include/hw/dma/pl080.h
 F: hw/dma/pl330.c
 F: hw/gpio/pl061.c
 F: hw/input/pl050.c
-- 
2.17.1

  parent reply	other threads:[~2018-08-09 13:01 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-09 13:00 [Qemu-devel] [PATCH 00/16] arm: Implement MPS2 watchdogs and DMA Peter Maydell
2018-08-09 13:01 ` [Qemu-devel] [PATCH 01/16] hw/watchdog/cmsdk_apb_watchdog: Implement CMSDK APB watchdog module Peter Maydell
2018-08-18  1:27   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2018-08-09 13:01 ` [Qemu-devel] [PATCH 02/16] nvic: Expose NMI line Peter Maydell
2018-08-10  5:05   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2018-08-09 13:01 ` [Qemu-devel] [PATCH 03/16] hw/arm/iotkit: Wire up the watchdogs Peter Maydell
2018-08-17 23:47   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2018-08-09 13:01 ` [Qemu-devel] [PATCH 04/16] hw/arm/iotkit: Wire up the S32KTIMER Peter Maydell
2018-08-17 23:49   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2018-08-09 13:01 ` [Qemu-devel] [PATCH 05/16] hw/misc/iotkit-sysctl: Implement IoTKit system control element Peter Maydell
2018-08-18  0:23   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2018-08-18 10:04     ` Peter Maydell
2018-08-18 19:54       ` Philippe Mathieu-Daudé
2018-08-09 13:01 ` [Qemu-devel] [PATCH 06/16] hw/misc/iotkit: Wire up the " Peter Maydell
2018-08-18  0:00   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2018-08-18  9:55     ` Peter Maydell
2018-08-18 15:06       ` Philippe Mathieu-Daudé
2018-08-09 13:01 ` [Qemu-devel] [PATCH 07/16] hw/misc/tz-msc: Model TrustZone Master Security Controller Peter Maydell
2018-08-18  1:15   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2018-08-09 13:01 ` [Qemu-devel] [PATCH 08/16] hw/misc/iotkit-secctl: Wire up registers for controlling MSCs Peter Maydell
2018-08-18  0:37   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2018-08-18 10:05     ` Peter Maydell
2018-08-18 15:42       ` Philippe Mathieu-Daudé
2018-08-09 13:01 ` [Qemu-devel] [PATCH 09/16] hw/arm/iotkit: Wire up the lines for MSCs Peter Maydell
2018-08-18  0:39   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2018-08-09 13:01 ` Peter Maydell [this message]
2018-08-10  5:18   ` [Qemu-devel] [Qemu-arm] [PATCH 10/16] hw/dma/pl080: Allow use as embedded-struct device Philippe Mathieu-Daudé
2018-08-10  5:27     ` Philippe Mathieu-Daudé
2018-08-10  9:03       ` Peter Maydell
2018-08-09 13:01 ` [Qemu-devel] [PATCH 11/16] hw/dma/pl080: Support all three interrupt lines Peter Maydell
2018-08-18  0:43   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2018-08-09 13:01 ` [Qemu-devel] [PATCH 12/16] hw/dma/pl080: Don't use CPU address space for DMA accesses Peter Maydell
2018-08-10  5:10   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2018-08-09 13:01 ` [Qemu-devel] [PATCH 13/16] hw/dma/pl080: Provide device reset function Peter Maydell
2018-08-10  5:11   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2018-08-09 13:01 ` [Qemu-devel] [PATCH 14/16] hw/dma/pl080: Correct bug in register address decode logic Peter Maydell
2018-08-15 14:39   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2018-08-15 15:31     ` Peter Maydell
2018-08-09 13:01 ` [Qemu-devel] [PATCH 15/16] hw/dma/pl080: Remove hw_error() if DMA is enabled Peter Maydell
2018-08-10  5:12   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2018-08-09 13:01 ` [Qemu-devel] [PATCH 16/16] hw/arm/mps2-tz: Create PL081s and MSCs Peter Maydell
2018-08-18  1:09   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2018-08-18 10:07     ` Peter Maydell
2018-08-16 18:02 ` [Qemu-devel] [Qemu-arm] [PATCH 00/16] arm: Implement MPS2 watchdogs and DMA Peter Maydell
2018-08-18  1:29   ` Philippe Mathieu-Daudé

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