[Qemu-devel] [PATCH 0/6] target/arm: More sve-ish fixes

[Qemu-devel] [PATCH 0/6] target/arm: More sve-ish fixes

[Richard Henderson]

All from problems reported by Laurent this week.  Five of them are
SVE related, but while trying to simplify one of the reports I
discovered that I had broken ARMv8.3 just before final commit.


r~


Richard Henderson (6):
  target/arm: Adjust FPCR_MASK for FZ16
  target/arm: Ignore float_flag_input_denormal from fp_status_f16
  target/arm: Use fp_status_fp16 for do_fmpa_zpzzz_h
  target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half
  target/arm: Fix aa64 FCADD and FCMLA decode
  softfloat: Fix missing inexact for floating-point add

 target/arm/cpu.h           |  2 +-
 fpu/softfloat.c            |  2 +-
 target/arm/helper.c        | 11 ++++++++++-
 target/arm/sve_helper.c    |  2 +-
 target/arm/translate-a64.c | 12 ++++++------
 target/arm/translate-sve.c |  4 ++--
 6 files changed, 21 insertions(+), 12 deletions(-)

-- 
2.17.1

[Qemu-devel] [PATCH 1/6] target/arm: Adjust FPCR_MASK for FZ16

[Richard Henderson]

When support for FZ16 was added, we failed to include the bit
within FPCR_MASK, which means that it could never be set.
Continue to zero FZ16 when ARMv8.2-FP16 is not enabled.

Fixes: d81ce0ef2c4
Cc: qemu-stable@nongnu.org (3.0.1)
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu.h    | 2 +-
 target/arm/helper.c | 5 +++++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 33d06f2340..0176716a70 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1279,7 +1279,7 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
  * we store the underlying state in fpscr and just mask on read/write.
  */
 #define FPSR_MASK 0xf800009f
-#define FPCR_MASK 0x07f79f00
+#define FPCR_MASK 0x07ff9f00
 
 #define FPCR_FZ16   (1 << 19)   /* ARMv8.2+, FP16 flush-to-zero */
 #define FPCR_FZ     (1 << 24)   /* Flush-to-zero enable bit */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 64ff71b722..452d5e182a 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11351,6 +11351,11 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
     int i;
     uint32_t changed;
 
+    /* When ARMv8.2-FP16 is not supported, FZ16 is RES0.  */
+    if (!arm_feature(env, ARM_FEATURE_V8_FP16)) {
+        val &= ~FPCR_FZ16;
+    }
+
     changed = env->vfp.xregs[ARM_VFP_FPSCR];
     env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
     env->vfp.vec_len = (val >> 16) & 7;
-- 
2.17.1

[Qemu-devel] [PATCH 2/6] target/arm: Ignore float_flag_input_denormal from fp_status_f16

[Richard Henderson]

When FZ is set, input_denormal exceptions are recognized, but this does
not happen with FZ16.  The softfloat code has no way to distinguish
these bits and will raise such exceptions into fp_status_f16.flags,
so ignore them when computing the accumulated flags.

Cc: qemu-stable@nongnu.org (3.0.1)
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/helper.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 452d5e182a..61454a77ec 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11314,9 +11314,13 @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
     fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
             | (env->vfp.vec_len << 16)
             | (env->vfp.vec_stride << 20);
+
     i = get_float_exception_flags(&env->vfp.fp_status);
     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
-    i |= get_float_exception_flags(&env->vfp.fp_status_f16);
+    /* FZ16 does not generate an input denormal exception.  */
+    i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
+          & ~float_flag_input_denormal);
+
     fpscr |= vfp_exceptbits_from_host(i);
     return fpscr;
 }
-- 
2.17.1

[Qemu-devel] [PATCH 3/6] target/arm: Use fp_status_fp16 for do_fmpa_zpzzz_h

[Richard Henderson]

This makes float16_muladd correctly use FZ16 not FZ.

Fixes: 6ceabaad110
Cc: qemu-stable@nongnu.org (3.0.1)
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/sve_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 5bae600d17..f8434e68f2 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -3398,7 +3398,7 @@ static void do_fmla_zpzzz_h(CPUARMState *env, void *vg, uint32_t desc,
                 e1 = *(uint16_t *)(vn + H1_2(i)) ^ neg1;
                 e2 = *(uint16_t *)(vm + H1_2(i));
                 e3 = *(uint16_t *)(va + H1_2(i)) ^ neg3;
-                r = float16_muladd(e1, e2, e3, 0, &env->vfp.fp_status);
+                r = float16_muladd(e1, e2, e3, 0, &env->vfp.fp_status_f16);
                 *(uint16_t *)(vd + H1_2(i)) = r;
             }
         } while (i & 63);
-- 
2.17.1

[Qemu-devel] [PATCH 4/6] target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half

[Richard Henderson]

We were using the wrong flush-to-zero bit for the non-half input.

Fixes: 46d33d1e3c9
Cc: qemu-stable@nongnu.org (3.0.1)
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/translate-sve.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 05ba0518c8..fe7aebdc19 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -4093,7 +4093,7 @@ static bool do_zpz_ptr(DisasContext *s, int rd, int rn, int pg,
 
 static bool trans_FCVT_sh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
 {
-    return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_sh);
+    return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sh);
 }
 
 static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
@@ -4103,7 +4103,7 @@ static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
 
 static bool trans_FCVT_dh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
 {
-    return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_dh);
+    return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_dh);
 }
 
 static bool trans_FCVT_hd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
-- 
2.17.1

[Qemu-devel] [PATCH 5/6] target/arm: Fix aa64 FCADD and FCMLA decode

[Richard Henderson]

These insns require u=1; failed to include that in the switch
cases.  This probably happened during one of the rebases just
before final commit.

Fixes: d17b7cdcf4e
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/translate-a64.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 4a0ca8c906..8a24278d79 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -11427,12 +11427,12 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
         }
         feature = ARM_FEATURE_V8_DOTPROD;
         break;
-    case 0x8: /* FCMLA, #0 */
-    case 0x9: /* FCMLA, #90 */
-    case 0xa: /* FCMLA, #180 */
-    case 0xb: /* FCMLA, #270 */
-    case 0xc: /* FCADD, #90 */
-    case 0xe: /* FCADD, #270 */
+    case 0x18: /* FCMLA, #0 */
+    case 0x19: /* FCMLA, #90 */
+    case 0x1a: /* FCMLA, #180 */
+    case 0x1b: /* FCMLA, #270 */
+    case 0x1c: /* FCADD, #90 */
+    case 0x1e: /* FCADD, #270 */
         if (size == 0
             || (size == 1 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))
             || (size == 3 && !is_q)) {
-- 
2.17.1

[Qemu-devel] [PATCH 6/6] softfloat: Fix missing inexact for floating-point add

[Richard Henderson]

For 0x1.0000000000003p+0 + 0x1.ffffffep+14 = 0x1.0001fffp+15
we dropped the sticky bit and so failed to raise inexact.

Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 fpu/softfloat.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 8cd2400081..7d63cffdeb 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -701,7 +701,7 @@ static FloatParts addsub_floats(FloatParts a, FloatParts b, bool subtract,
             }
             a.frac += b.frac;
             if (a.frac & DECOMPOSED_OVERFLOW_BIT) {
-                a.frac >>= 1;
+                shift64RightJamming(a.frac, 1, &a.frac);
                 a.exp += 1;
             }
             return a;
-- 
2.17.1

Re: [Qemu-devel] [PATCH 1/6] target/arm: Adjust FPCR_MASK for FZ16

[Laurent Desnogues]

On Fri, Aug 10, 2018 at 9:31 PM, Richard Henderson
<richard.henderson@linaro.org> wrote:
> When support for FZ16 was added, we failed to include the bit
> within FPCR_MASK, which means that it could never be set.
> Continue to zero FZ16 when ARMv8.2-FP16 is not enabled.
>
> Fixes: d81ce0ef2c4
> Cc: qemu-stable@nongnu.org (3.0.1)
> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Laurent

> ---
>  target/arm/cpu.h    | 2 +-
>  target/arm/helper.c | 5 +++++
>  2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 33d06f2340..0176716a70 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1279,7 +1279,7 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
>   * we store the underlying state in fpscr and just mask on read/write.
>   */
>  #define FPSR_MASK 0xf800009f
> -#define FPCR_MASK 0x07f79f00
> +#define FPCR_MASK 0x07ff9f00
>
>  #define FPCR_FZ16   (1 << 19)   /* ARMv8.2+, FP16 flush-to-zero */
>  #define FPCR_FZ     (1 << 24)   /* Flush-to-zero enable bit */
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 64ff71b722..452d5e182a 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -11351,6 +11351,11 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
>      int i;
>      uint32_t changed;
>
> +    /* When ARMv8.2-FP16 is not supported, FZ16 is RES0.  */
> +    if (!arm_feature(env, ARM_FEATURE_V8_FP16)) {
> +        val &= ~FPCR_FZ16;
> +    }
> +
>      changed = env->vfp.xregs[ARM_VFP_FPSCR];
>      env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
>      env->vfp.vec_len = (val >> 16) & 7;
> --
> 2.17.1
>

Re: [Qemu-devel] [PATCH 2/6] target/arm: Ignore float_flag_input_denormal from fp_status_f16

[Laurent Desnogues]

On Fri, Aug 10, 2018 at 9:31 PM, Richard Henderson
<richard.henderson@linaro.org> wrote:
> When FZ is set, input_denormal exceptions are recognized, but this does
> not happen with FZ16.  The softfloat code has no way to distinguish
> these bits and will raise such exceptions into fp_status_f16.flags,
> so ignore them when computing the accumulated flags.
>
> Cc: qemu-stable@nongnu.org (3.0.1)
> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Laurent

> ---
>  target/arm/helper.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 452d5e182a..61454a77ec 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -11314,9 +11314,13 @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
>      fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
>              | (env->vfp.vec_len << 16)
>              | (env->vfp.vec_stride << 20);
> +
>      i = get_float_exception_flags(&env->vfp.fp_status);
>      i |= get_float_exception_flags(&env->vfp.standard_fp_status);
> -    i |= get_float_exception_flags(&env->vfp.fp_status_f16);
> +    /* FZ16 does not generate an input denormal exception.  */
> +    i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
> +          & ~float_flag_input_denormal);
> +
>      fpscr |= vfp_exceptbits_from_host(i);
>      return fpscr;
>  }
> --
> 2.17.1
>

Re: [Qemu-devel] [PATCH 3/6] target/arm: Use fp_status_fp16 for do_fmpa_zpzzz_h

[Laurent Desnogues]

On Fri, Aug 10, 2018 at 9:31 PM, Richard Henderson
<richard.henderson@linaro.org> wrote:
> This makes float16_muladd correctly use FZ16 not FZ.
>
> Fixes: 6ceabaad110
> Cc: qemu-stable@nongnu.org (3.0.1)
> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Laurent

> ---
>  target/arm/sve_helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
> index 5bae600d17..f8434e68f2 100644
> --- a/target/arm/sve_helper.c
> +++ b/target/arm/sve_helper.c
> @@ -3398,7 +3398,7 @@ static void do_fmla_zpzzz_h(CPUARMState *env, void *vg, uint32_t desc,
>                  e1 = *(uint16_t *)(vn + H1_2(i)) ^ neg1;
>                  e2 = *(uint16_t *)(vm + H1_2(i));
>                  e3 = *(uint16_t *)(va + H1_2(i)) ^ neg3;
> -                r = float16_muladd(e1, e2, e3, 0, &env->vfp.fp_status);
> +                r = float16_muladd(e1, e2, e3, 0, &env->vfp.fp_status_f16);
>                  *(uint16_t *)(vd + H1_2(i)) = r;
>              }
>          } while (i & 63);
> --
> 2.17.1
>

Re: [Qemu-devel] [PATCH 4/6] target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half

[Laurent Desnogues]

On Fri, Aug 10, 2018 at 9:31 PM, Richard Henderson
<richard.henderson@linaro.org> wrote:
> We were using the wrong flush-to-zero bit for the non-half input.
>
> Fixes: 46d33d1e3c9
> Cc: qemu-stable@nongnu.org (3.0.1)
> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Laurent

> ---
>  target/arm/translate-sve.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
> index 05ba0518c8..fe7aebdc19 100644
> --- a/target/arm/translate-sve.c
> +++ b/target/arm/translate-sve.c
> @@ -4093,7 +4093,7 @@ static bool do_zpz_ptr(DisasContext *s, int rd, int rn, int pg,
>
>  static bool trans_FCVT_sh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
>  {
> -    return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_sh);
> +    return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sh);
>  }
>
>  static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
> @@ -4103,7 +4103,7 @@ static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
>
>  static bool trans_FCVT_dh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
>  {
> -    return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_dh);
> +    return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_dh);
>  }
>
>  static bool trans_FCVT_hd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
> --
> 2.17.1
>

Re: [Qemu-devel] [PATCH 6/6] softfloat: Fix missing inexact for floating-point add

[Laurent Desnogues]

On Fri, Aug 10, 2018 at 9:31 PM, Richard Henderson
<richard.henderson@linaro.org> wrote:
> For 0x1.0000000000003p+0 + 0x1.ffffffep+14 = 0x1.0001fffp+15
> we dropped the sticky bit and so failed to raise inexact.
>
> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Laurent

> ---
>  fpu/softfloat.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/fpu/softfloat.c b/fpu/softfloat.c
> index 8cd2400081..7d63cffdeb 100644
> --- a/fpu/softfloat.c
> +++ b/fpu/softfloat.c
> @@ -701,7 +701,7 @@ static FloatParts addsub_floats(FloatParts a, FloatParts b, bool subtract,
>              }
>              a.frac += b.frac;
>              if (a.frac & DECOMPOSED_OVERFLOW_BIT) {
> -                a.frac >>= 1;
> +                shift64RightJamming(a.frac, 1, &a.frac);
>                  a.exp += 1;
>              }
>              return a;
> --
> 2.17.1
>

Re: [Qemu-devel] [PATCH 5/6] target/arm: Fix aa64 FCADD and FCMLA decode

[Laurent Desnogues]

On Fri, Aug 10, 2018 at 9:31 PM, Richard Henderson
<richard.henderson@linaro.org> wrote:
> These insns require u=1; failed to include that in the switch
> cases.  This probably happened during one of the rebases just
> before final commit.
>
> Fixes: d17b7cdcf4e
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Laurent

> ---
>  target/arm/translate-a64.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index 4a0ca8c906..8a24278d79 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -11427,12 +11427,12 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
>          }
>          feature = ARM_FEATURE_V8_DOTPROD;
>          break;
> -    case 0x8: /* FCMLA, #0 */
> -    case 0x9: /* FCMLA, #90 */
> -    case 0xa: /* FCMLA, #180 */
> -    case 0xb: /* FCMLA, #270 */
> -    case 0xc: /* FCADD, #90 */
> -    case 0xe: /* FCADD, #270 */
> +    case 0x18: /* FCMLA, #0 */
> +    case 0x19: /* FCMLA, #90 */
> +    case 0x1a: /* FCMLA, #180 */
> +    case 0x1b: /* FCMLA, #270 */
> +    case 0x1c: /* FCADD, #90 */
> +    case 0x1e: /* FCADD, #270 */
>          if (size == 0
>              || (size == 1 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))
>              || (size == 3 && !is_q)) {
> --
> 2.17.1
>

Re: [Qemu-devel] [PATCH 0/6] target/arm: More sve-ish fixes

[Peter Maydell]

On 10 August 2018 at 20:31, Richard Henderson
<richard.henderson@linaro.org> wrote:
> All from problems reported by Laurent this week.  Five of them are
> SVE related, but while trying to simplify one of the reports I
> discovered that I had broken ARMv8.3 just before final commit.
>
>
> r~
>
>
> Richard Henderson (6):
>   target/arm: Adjust FPCR_MASK for FZ16
>   target/arm: Ignore float_flag_input_denormal from fp_status_f16
>   target/arm: Use fp_status_fp16 for do_fmpa_zpzzz_h
>   target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half
>   target/arm: Fix aa64 FCADD and FCMLA decode
>   softfloat: Fix missing inexact for floating-point add



Applied to target-arm.next, thanks.

-- PMM