From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 21/45] intc/arm_gic: Implement virtualization extensions in gic_(activate_irq|drop_prio)
Date: Tue, 14 Aug 2018 19:17:51 +0100 [thread overview]
Message-ID: <20180814181815.23348-22-peter.maydell@linaro.org> (raw)
In-Reply-To: <20180814181815.23348-1-peter.maydell@linaro.org>
From: Luc Michel <luc.michel@greensocs.com>
Implement virtualization extensions in gic_activate_irq() and
gic_drop_prio() and in gic_get_prio_from_apr_bits() called by
gic_drop_prio().
When the current CPU is a vCPU:
- Use GIC_VIRT_MIN_BPR and GIC_VIRT_NR_APRS instead of their non-virt
counterparts,
- the vCPU APR is stored in the virtual interface, in h_apr.
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180727095421.386-11-luc.michel@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gic.c | 50 +++++++++++++++++++++++++++++++++++------------
1 file changed, 38 insertions(+), 12 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 26ed7ea58ab..de73dc9f54b 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -276,16 +276,23 @@ static void gic_activate_irq(GICState *s, int cpu, int irq)
* and update the running priority.
*/
int prio = gic_get_group_priority(s, cpu, irq);
- int preemption_level = prio >> (GIC_MIN_BPR + 1);
+ int min_bpr = gic_is_vcpu(cpu) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR;
+ int preemption_level = prio >> (min_bpr + 1);
int regno = preemption_level / 32;
int bitno = preemption_level % 32;
+ uint32_t *papr = NULL;
- if (gic_has_groups(s) && gic_test_group(s, irq, cpu)) {
- s->nsapr[regno][cpu] |= (1 << bitno);
+ if (gic_is_vcpu(cpu)) {
+ assert(regno == 0);
+ papr = &s->h_apr[gic_get_vcpu_real_id(cpu)];
+ } else if (gic_has_groups(s) && gic_test_group(s, irq, cpu)) {
+ papr = &s->nsapr[regno][cpu];
} else {
- s->apr[regno][cpu] |= (1 << bitno);
+ papr = &s->apr[regno][cpu];
}
+ *papr |= (1 << bitno);
+
s->running_priority[cpu] = prio;
gic_set_active(s, irq, cpu);
}
@@ -296,6 +303,16 @@ static int gic_get_prio_from_apr_bits(GICState *s, int cpu)
* on the set bits in the Active Priority Registers.
*/
int i;
+
+ if (gic_is_vcpu(cpu)) {
+ uint32_t apr = s->h_apr[gic_get_vcpu_real_id(cpu)];
+ if (apr) {
+ return ctz32(apr) << (GIC_VIRT_MIN_BPR + 1);
+ } else {
+ return 0x100;
+ }
+ }
+
for (i = 0; i < GIC_NR_APRS; i++) {
uint32_t apr = s->apr[i][cpu] | s->nsapr[i][cpu];
if (!apr) {
@@ -324,16 +341,25 @@ static void gic_drop_prio(GICState *s, int cpu, int group)
* running priority will be wrong, so interrupts that should preempt
* might not do so, and interrupts that should not preempt might do so.
*/
- int i;
+ if (gic_is_vcpu(cpu)) {
+ int rcpu = gic_get_vcpu_real_id(cpu);
- for (i = 0; i < GIC_NR_APRS; i++) {
- uint32_t *papr = group ? &s->nsapr[i][cpu] : &s->apr[i][cpu];
- if (!*papr) {
- continue;
+ if (s->h_apr[rcpu]) {
+ /* Clear lowest set bit */
+ s->h_apr[rcpu] &= s->h_apr[rcpu] - 1;
+ }
+ } else {
+ int i;
+
+ for (i = 0; i < GIC_NR_APRS; i++) {
+ uint32_t *papr = group ? &s->nsapr[i][cpu] : &s->apr[i][cpu];
+ if (!*papr) {
+ continue;
+ }
+ /* Clear lowest set bit */
+ *papr &= *papr - 1;
+ break;
}
- /* Clear lowest set bit */
- *papr &= *papr - 1;
- break;
}
s->running_priority[cpu] = gic_get_prio_from_apr_bits(s, cpu);
--
2.18.0
next prev parent reply other threads:[~2018-08-14 18:21 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-14 18:17 [Qemu-devel] [PULL 00/45] target-arm queue Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 01/45] target/arm: Forbid unprivileged mode for M Baseline Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 02/45] nvic: Handle ARMv6-M SCS reserved registers Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 03/45] arm: Add ARMv6-M programmer's model support Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 04/45] nvic: Change NVIC to support ARMv6-M Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 05/45] accel/tcg: Pass read access type through to io_readx() Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 06/45] accel/tcg: Handle get_page_addr_code() returning -1 in hashtable lookups Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 07/45] accel/tcg: Handle get_page_addr_code() returning -1 in tb_check_watchpoint() Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 08/45] accel/tcg: tb_gen_code(): Create single-insn TB for execution from non-RAM Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 09/45] accel/tcg: Return -1 for execution from MMIO regions in get_page_addr_code() Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 10/45] target/arm: Allow execution from small regions Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 11/45] accel/tcg: Check whether TLB entry is RAM consistently with how we set it up Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 12/45] intc/arm_gic: Refactor operations on the distributor Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 13/45] intc/arm_gic: Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 14/45] intc/arm_gic: Remove some dead code and put some functions static Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 15/45] vmstate.h: Provide VMSTATE_UINT16_SUB_ARRAY Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 16/45] intc/arm_gic: Add the virtualization extensions to the GIC state Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 17/45] intc/arm_gic: Add virtual interface register definitions Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 18/45] intc/arm_gic: Add virtualization extensions helper macros and functions Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 19/45] intc/arm_gic: Refactor secure/ns access check in the CPU interface Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 20/45] intc/arm_gic: Add virtualization enabled IRQ helper functions Peter Maydell
2018-08-14 18:17 ` Peter Maydell [this message]
2018-08-14 18:17 ` [Qemu-devel] [PULL 22/45] intc/arm_gic: Implement virtualization extensions in gic_acknowledge_irq Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 23/45] intc/arm_gic: Implement virtualization extensions in gic_(deactivate|complete_irq) Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 24/45] intc/arm_gic: Implement virtualization extensions in gic_cpu_(read|write) Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 25/45] intc/arm_gic: Wire the vCPU interface Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 26/45] intc/arm_gic: Implement the virtual interface registers Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 27/45] intc/arm_gic: Implement gic_update_virt() function Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 28/45] intc/arm_gic: Implement maintenance interrupt generation Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 29/45] intc/arm_gic: Improve traces Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 30/45] xlnx-zynqmp: Improve GIC wiring and MMIO mapping Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 31/45] arm/virt: Add support for GICv2 virtualization extensions Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 32/45] arm: Fix return code of arm_load_elf Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 33/45] target/arm: Mask virtual interrupts if HCR_EL2.TGE is set Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 34/45] target/arm: Honour HCR_EL2.TGE and MDCR_EL2.TDE in debug register access checks Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 35/45] target/arm: Honour HCR_EL2.TGE when raising synchronous exceptions Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 36/45] target/arm: Provide accessor functions for HCR_EL2.{IMO, FMO, AMO} Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 37/45] target/arm: Treat SCTLR_EL1.M as if it were zero when HCR_EL2.TGE is set Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 38/45] target/arm: Improve exception-taken logging Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 39/45] target/arm: Initialize exc_secure correctly in do_v7m_exception_exit() Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 40/45] target/arm: Restore M-profile CONTROL.SPSEL before any tailchaining Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 41/45] target/arm: Implement tailchaining for M profile cores Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 42/45] target/arm: Fix sign of sve_cmpeq_ppzw/sve_cmpne_ppzw Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 43/45] target/arm: Fix typo in do_sat_addsub_64 Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 44/45] target/arm: Reorganize SVE WHILE Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 45/45] target/arm: Fix typo in helper_sve_movz_d Peter Maydell
2018-08-15 12:29 ` [Qemu-devel] [PULL 00/45] target-arm queue Peter Maydell
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