From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 07/45] accel/tcg: Handle get_page_addr_code() returning -1 in tb_check_watchpoint()
Date: Tue, 14 Aug 2018 19:17:37 +0100 [thread overview]
Message-ID: <20180814181815.23348-8-peter.maydell@linaro.org> (raw)
In-Reply-To: <20180814181815.23348-1-peter.maydell@linaro.org>
When we support execution from non-RAM MMIO regions, get_page_addr_code()
will return -1 to indicate that there is no RAM at the requested address.
Handle this in tb_check_watchpoint() -- if the exception happened for a
PC which doesn't correspond to RAM then there is no need to invalidate
any TBs, because the one-instruction TB will not have been cached.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20180710160013.26559-4-peter.maydell@linaro.org
---
accel/tcg/translate-all.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 1571987113b..ff7d0145f46 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -2121,7 +2121,9 @@ void tb_check_watchpoint(CPUState *cpu)
cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
addr = get_page_addr_code(env, pc);
- tb_invalidate_phys_range(addr, addr + 1);
+ if (addr != -1) {
+ tb_invalidate_phys_range(addr, addr + 1);
+ }
}
}
--
2.18.0
next prev parent reply other threads:[~2018-08-14 18:21 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-14 18:17 [Qemu-devel] [PULL 00/45] target-arm queue Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 01/45] target/arm: Forbid unprivileged mode for M Baseline Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 02/45] nvic: Handle ARMv6-M SCS reserved registers Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 03/45] arm: Add ARMv6-M programmer's model support Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 04/45] nvic: Change NVIC to support ARMv6-M Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 05/45] accel/tcg: Pass read access type through to io_readx() Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 06/45] accel/tcg: Handle get_page_addr_code() returning -1 in hashtable lookups Peter Maydell
2018-08-14 18:17 ` Peter Maydell [this message]
2018-08-14 18:17 ` [Qemu-devel] [PULL 08/45] accel/tcg: tb_gen_code(): Create single-insn TB for execution from non-RAM Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 09/45] accel/tcg: Return -1 for execution from MMIO regions in get_page_addr_code() Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 10/45] target/arm: Allow execution from small regions Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 11/45] accel/tcg: Check whether TLB entry is RAM consistently with how we set it up Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 12/45] intc/arm_gic: Refactor operations on the distributor Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 13/45] intc/arm_gic: Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 14/45] intc/arm_gic: Remove some dead code and put some functions static Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 15/45] vmstate.h: Provide VMSTATE_UINT16_SUB_ARRAY Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 16/45] intc/arm_gic: Add the virtualization extensions to the GIC state Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 17/45] intc/arm_gic: Add virtual interface register definitions Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 18/45] intc/arm_gic: Add virtualization extensions helper macros and functions Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 19/45] intc/arm_gic: Refactor secure/ns access check in the CPU interface Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 20/45] intc/arm_gic: Add virtualization enabled IRQ helper functions Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 21/45] intc/arm_gic: Implement virtualization extensions in gic_(activate_irq|drop_prio) Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 22/45] intc/arm_gic: Implement virtualization extensions in gic_acknowledge_irq Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 23/45] intc/arm_gic: Implement virtualization extensions in gic_(deactivate|complete_irq) Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 24/45] intc/arm_gic: Implement virtualization extensions in gic_cpu_(read|write) Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 25/45] intc/arm_gic: Wire the vCPU interface Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 26/45] intc/arm_gic: Implement the virtual interface registers Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 27/45] intc/arm_gic: Implement gic_update_virt() function Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 28/45] intc/arm_gic: Implement maintenance interrupt generation Peter Maydell
2018-08-14 18:17 ` [Qemu-devel] [PULL 29/45] intc/arm_gic: Improve traces Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 30/45] xlnx-zynqmp: Improve GIC wiring and MMIO mapping Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 31/45] arm/virt: Add support for GICv2 virtualization extensions Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 32/45] arm: Fix return code of arm_load_elf Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 33/45] target/arm: Mask virtual interrupts if HCR_EL2.TGE is set Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 34/45] target/arm: Honour HCR_EL2.TGE and MDCR_EL2.TDE in debug register access checks Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 35/45] target/arm: Honour HCR_EL2.TGE when raising synchronous exceptions Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 36/45] target/arm: Provide accessor functions for HCR_EL2.{IMO, FMO, AMO} Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 37/45] target/arm: Treat SCTLR_EL1.M as if it were zero when HCR_EL2.TGE is set Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 38/45] target/arm: Improve exception-taken logging Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 39/45] target/arm: Initialize exc_secure correctly in do_v7m_exception_exit() Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 40/45] target/arm: Restore M-profile CONTROL.SPSEL before any tailchaining Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 41/45] target/arm: Implement tailchaining for M profile cores Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 42/45] target/arm: Fix sign of sve_cmpeq_ppzw/sve_cmpne_ppzw Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 43/45] target/arm: Fix typo in do_sat_addsub_64 Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 44/45] target/arm: Reorganize SVE WHILE Peter Maydell
2018-08-14 18:18 ` [Qemu-devel] [PULL 45/45] target/arm: Fix typo in helper_sve_movz_d Peter Maydell
2018-08-15 12:29 ` [Qemu-devel] [PULL 00/45] target-arm queue Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180814181815.23348-8-peter.maydell@linaro.org \
--to=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).