[Qemu-devel] [PATCH 0/9] arm: Wire up GICv2 virt support on A15/A7 boards

[Qemu-devel] [PATCH 0/9] arm: Wire up GICv2 virt support on A15/A7 boards

[Peter Maydell]

This patchset wires up the GICv2 virtualization support
on all our Cortex-A15 and Cortex-A7 boards.

These boards fall into various categories:
 * virt: already done in master
 * highbank, imx6, imx7: the CPU is configured to always
   have EL3, so we unconditionally allow EL2 to be enabled too
   and just need to wire up the GIC VIRQ/VFIQ lines
 * raspi2: has a non-standard interrupt controller, not a GIC,
   so we enable EL2 but there's no wiring to be done
 * vexpress-a15: is configurable to have EL3 or not; we add
   extra configuration so the user can add EL2 or not, using
   a machine property "virtualization", paralleling the
   existing "secure" property.

In all cases, most of the handling of mapping extra register
ranges into the address space and wiring up the maintenance
irq is dealt with by the a15mpcore container object.

Adding EL2 support has the potential to confuse older guests,
because it will mean that we'll boot into Hyp mode by default
if we're booting the kernel non-secure. But the Linux kernel
booting specification has required that for a long time now.

I had to fix one issue with an oversized memory region in
the GIC; there's also a documentation-comment patch in there
which records some stuff I had to figure out in trying to
map the right memory regions in the right places.

None of this code actually does anything (except provide a
property that doesn't do anything on vexpress-a15) until we
actually set the ARM_FEATURE_EL2 bit for A15 and A7.

thanks
-- PMM


Peter Maydell (9):
  hw/intc/arm_gic: Document QEMU interface
  hw/intc/arm_gic: Make per-cpu GICH memory regions 0x200 bytes large
  hw/arm/vexpress: Connect VIRQ and VFIQ
  hw/arm/highbank: Connect VIRQ and VFIQ
  hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ
  hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ
  hw/cpu/a15mpcore: If CPU has EL2, enable it on the GIC and wire it up
  hw/arm/vexpress: Don't set info->secure_boot if CPU doesn't have EL3
  hw/arm/vexpress: Add "virtualization" property controlling presence of
    EL2

 include/hw/intc/arm_gic.h | 35 +++++++++++++++++++++
 hw/arm/fsl-imx6ul.c       |  4 +++
 hw/arm/fsl-imx7.c         |  4 +++
 hw/arm/highbank.c         |  6 ++++
 hw/arm/vexpress.c         | 64 ++++++++++++++++++++++++++++++++++++---
 hw/cpu/a15mpcore.c        | 31 +++++++++++++++++--
 hw/intc/arm_gic.c         |  2 +-
 7 files changed, 137 insertions(+), 9 deletions(-)

-- 
2.18.0

[Qemu-devel] [PATCH 1/9] hw/intc/arm_gic: Document QEMU interface

[Peter Maydell]

The GICv2's QEMU interface (sysbus MMIO regions, IRQs,
etc) is now quite complicated with the addition of the
virtualization extensions. Add a comment in the header
file which documents it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
I needed to write this out to figure out what I was
connecting to what in the a15mpcore object :-)
---
 include/hw/intc/arm_gic.h | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h
index 42bb535fd45..989bc837606 100644
--- a/include/hw/intc/arm_gic.h
+++ b/include/hw/intc/arm_gic.h
@@ -18,6 +18,41 @@
  * with this program; if not, see <http://www.gnu.org/licenses/>.
  */
 
+/*
+ * QEMU interface:
+ *  + QOM property "num-cpu": number of CPUs to support
+ *  + QOM property "num-irq": number of IRQs (including both SPIs and PPIs)
+ *  + QOM property "revision": GIC version (1 or 2), or 0 for the 11MPCore GIC
+ *  + QOM property "has-security-extensions": set true if the GIC should
+ *    implement the security extensions
+ *  + QOM property "has-virtualization-extensions": set true if the GIC should
+ *    implement the virtualization extensions
+ *  + unnamed GPIO inputs: (where P is number of PPIs, i.e. num-irq - 32)
+ *    [0..P-1]  SPIs
+ *    [P..P+31] PPIs for CPU 0
+ *    [P+32..P+63] PPIs for CPU 1
+ *    ...
+ *  + sysbus IRQ 0 : IRQ
+ *  + sysbus IRQ 1 : FIQ
+ *  + sysbus IRQ 2 : VIRQ (exists even if virt extensions not present)
+ *  + sysbus IRQ 3 : VFIQ (exists even if virt extensions not present)
+ *  + sysbus IRQ 4 : maintenance IRQ for CPU i/f 0 (only if virt extns present)
+ *  + sysbus IRQ 5 : maintenance IRQ for CPU i/f 1 (only if virt extns present)
+ *    ...
+ *  + sysbus MMIO regions: (in order; numbers will vary depending on
+ *    whether virtualization extensions are present and on number of cores)
+ *    - distributor registers (GICD*)
+ *    - CPU interface for the accessing core (GICC*)
+ *    - virtual interface control registers (GICH*) (only if virt extns present)
+ *    - virtual CPU interface for the accessing core (GICV*) (only if virt)
+ *    - CPU 0 CPU interface registers
+ *    - CPU 1 CPU interface registers
+ *      ...
+ *    - CPU 0 VCPU interface registers (only if virt extns present)
+ *    - CPU 1 VCPU interface registers (only if virt extns present)
+ *      ...
+ */
+
 #ifndef HW_ARM_GIC_H
 #define HW_ARM_GIC_H
 
-- 
2.18.0

Re: [Qemu-devel] [PATCH 1/9] hw/intc/arm_gic: Document QEMU interface

[Luc Michel]

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On 8/21/18 3:28 PM, Peter Maydell wrote:
> The GICv2's QEMU interface (sysbus MMIO regions, IRQs,
> etc) is now quite complicated with the addition of the
> virtualization extensions. Add a comment in the header
> file which documents it.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> I needed to write this out to figure out what I was
> connecting to what in the a15mpcore object :-)
> ---
>  include/hw/intc/arm_gic.h | 35 +++++++++++++++++++++++++++++++++++
>  1 file changed, 35 insertions(+)
> 
> diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h
> index 42bb535fd45..989bc837606 100644
> --- a/include/hw/intc/arm_gic.h
> +++ b/include/hw/intc/arm_gic.h
> @@ -18,6 +18,41 @@
>   * with this program; if not, see <http://www.gnu.org/licenses/>.
>   */
>  
> +/*
> + * QEMU interface:
> + *  + QOM property "num-cpu": number of CPUs to support
> + *  + QOM property "num-irq": number of IRQs (including both SPIs and PPIs)
> + *  + QOM property "revision": GIC version (1 or 2), or 0 for the 11MPCore GIC
> + *  + QOM property "has-security-extensions": set true if the GIC should
> + *    implement the security extensions
> + *  + QOM property "has-virtualization-extensions": set true if the GIC should
> + *    implement the virtualization extensions
> + *  + unnamed GPIO inputs: (where P is number of PPIs, i.e. num-irq - 32)
"where P is the number of SPIs"
> + *    [0..P-1]  SPIs
> + *    [P..P+31] PPIs for CPU 0
> + *    [P+32..P+63] PPIs for CPU 1
> + *    ...
> + *  + sysbus IRQ 0 : IRQ
> + *  + sysbus IRQ 1 : FIQ
> + *  + sysbus IRQ 2 : VIRQ (exists even if virt extensions not present)
> + *  + sysbus IRQ 3 : VFIQ (exists even if virt extensions not present)
> + *  + sysbus IRQ 4 : maintenance IRQ for CPU i/f 0 (only if virt extns present)
> + *  + sysbus IRQ 5 : maintenance IRQ for CPU i/f 1 (only if virt extns present)
I think it's more like

For a GIC supporting N CPUs:
  + sysbus IRQ 0: IRQ for CPU 0
  + ...
  + sysbus IRQ N-1: IRQ for CPU N-1

  + sysbus IRQ N: FIQ for CPU 0
  + ...
  + sysbus IRQ 2*N-1: FIQ for CPU N-1

  + sysbus IRQ 2*N: VIRQ for CPU 0
  + ...
  + sysbus IRQ 3*N-1: VIRQ for CPU N-1

  + sysbus IRQ 3*N: VFIQ for CPU 0
  + ...
  + sysbus IRQ 4*N-1: VFIQ for CPU N-1

  + sysbus IRQ 4*N: maintenance IRQ for CPU i/f 0 (only if virt extns
present)
  + ...
  + sysbus IRQ 5*N-1: maintenance IRQ for CPU i/f N-1 (only if virt
extns present)

> + *    ...
> + *  + sysbus MMIO regions: (in order; numbers will vary depending on
> + *    whether virtualization extensions are present and on number of cores)
> + *    - distributor registers (GICD*)
> + *    - CPU interface for the accessing core (GICC*)
> + *    - virtual interface control registers (GICH*) (only if virt extns present)
> + *    - virtual CPU interface for the accessing core (GICV*) (only if virt)
> + *    - CPU 0 CPU interface registers
> + *    - CPU 1 CPU interface registers
> + *      ...
> + *    - CPU 0 VCPU interface registers (only if virt extns present)
CPU 0 virtual interface (GICH*)
> + *    - CPU 1 VCPU interface registers (only if virt extns present)
CPU 1 virtual interface (GICH*)
> + *      ...> + */
> +
>  #ifndef HW_ARM_GIC_H
>  #define HW_ARM_GIC_H
>  
> 


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Re: [Qemu-devel] [PATCH 1/9] hw/intc/arm_gic: Document QEMU interface

[Peter Maydell]

On 22 August 2018 at 09:15, Luc Michel <luc.michel@greensocs.com> wrote:
>
>
> On 8/21/18 3:28 PM, Peter Maydell wrote:
>> The GICv2's QEMU interface (sysbus MMIO regions, IRQs,
>> etc) is now quite complicated with the addition of the
>> virtualization extensions. Add a comment in the header
>> file which documents it.
>>
>> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
>> ---
>> I needed to write this out to figure out what I was
>> connecting to what in the a15mpcore object :-)
>> ---
>>  include/hw/intc/arm_gic.h | 35 +++++++++++++++++++++++++++++++++++
>>  1 file changed, 35 insertions(+)
>>
>> diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h
>> index 42bb535fd45..989bc837606 100644
>> --- a/include/hw/intc/arm_gic.h
>> +++ b/include/hw/intc/arm_gic.h
>> @@ -18,6 +18,41 @@
>>   * with this program; if not, see <http://www.gnu.org/licenses/>.
>>   */
>>
>> +/*
>> + * QEMU interface:
>> + *  + QOM property "num-cpu": number of CPUs to support
>> + *  + QOM property "num-irq": number of IRQs (including both SPIs and PPIs)
>> + *  + QOM property "revision": GIC version (1 or 2), or 0 for the 11MPCore GIC
>> + *  + QOM property "has-security-extensions": set true if the GIC should
>> + *    implement the security extensions
>> + *  + QOM property "has-virtualization-extensions": set true if the GIC should
>> + *    implement the virtualization extensions
>> + *  + unnamed GPIO inputs: (where P is number of PPIs, i.e. num-irq - 32)
> "where P is the number of SPIs"
>> + *    [0..P-1]  SPIs
>> + *    [P..P+31] PPIs for CPU 0
>> + *    [P+32..P+63] PPIs for CPU 1
>> + *    ...
>> + *  + sysbus IRQ 0 : IRQ
>> + *  + sysbus IRQ 1 : FIQ
>> + *  + sysbus IRQ 2 : VIRQ (exists even if virt extensions not present)
>> + *  + sysbus IRQ 3 : VFIQ (exists even if virt extensions not present)
>> + *  + sysbus IRQ 4 : maintenance IRQ for CPU i/f 0 (only if virt extns present)
>> + *  + sysbus IRQ 5 : maintenance IRQ for CPU i/f 1 (only if virt extns present)
> I think it's more like
>
> For a GIC supporting N CPUs:
>   + sysbus IRQ 0: IRQ for CPU 0
>   + ...
>   + sysbus IRQ N-1: IRQ for CPU N-1
>
>   + sysbus IRQ N: FIQ for CPU 0
>   + ...
>   + sysbus IRQ 2*N-1: FIQ for CPU N-1
>
>   + sysbus IRQ 2*N: VIRQ for CPU 0
>   + ...
>   + sysbus IRQ 3*N-1: VIRQ for CPU N-1
>
>   + sysbus IRQ 3*N: VFIQ for CPU 0
>   + ...
>   + sysbus IRQ 4*N-1: VFIQ for CPU N-1
>
>   + sysbus IRQ 4*N: maintenance IRQ for CPU i/f 0 (only if virt extns
> present)
>   + ...
>   + sysbus IRQ 5*N-1: maintenance IRQ for CPU i/f N-1 (only if virt
> extns present)

Yes, indeed. Since this is just a comment patch, I'll apply
2-9 from this series to target-arm.next and respin this patch.
Thanks for the review.

-- PMM

[Qemu-devel] [PATCH 2/9] hw/intc/arm_gic: Make per-cpu GICH memory regions 0x200 bytes large

[Peter Maydell]

Reduce the size of the per-cpu GICH memory regions from 0x1000
to 0x200. The registers only cover 0x200 bytes, and the Cortex-A15
wants to map them at a spacing of 0x200 bytes apart. Having the
region be too large interferes with mapping them like that, so
reduce it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index c1b35fc1ee2..542b4b93eab 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -2084,7 +2084,7 @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
         for (i = 0; i < s->num_cpu; i++) {
             memory_region_init_io(&s->vifaceiomem[i + 1], OBJECT(s),
                                   &gic_viface_ops, &s->backref[i],
-                                  "gic_viface", 0x1000);
+                                  "gic_viface", 0x200);
             sysbus_init_mmio(sbd, &s->vifaceiomem[i + 1]);
         }
     }
-- 
2.18.0

Re: [Qemu-devel] [PATCH 2/9] hw/intc/arm_gic: Make per-cpu GICH memory regions 0x200 bytes large

[Luc Michel]

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On 8/21/18 3:28 PM, Peter Maydell wrote:
> Reduce the size of the per-cpu GICH memory regions from 0x1000
> to 0x200. The registers only cover 0x200 bytes, and the Cortex-A15
> wants to map them at a spacing of 0x200 bytes apart. Having the
> region be too large interferes with mapping them like that, so
> reduce it.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-By: Luc Michel <luc.michel@greensocs.com>

> ---
>  hw/intc/arm_gic.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
> index c1b35fc1ee2..542b4b93eab 100644
> --- a/hw/intc/arm_gic.c
> +++ b/hw/intc/arm_gic.c
> @@ -2084,7 +2084,7 @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
>          for (i = 0; i < s->num_cpu; i++) {
>              memory_region_init_io(&s->vifaceiomem[i + 1], OBJECT(s),
>                                    &gic_viface_ops, &s->backref[i],
> -                                  "gic_viface", 0x1000);
> +                                  "gic_viface", 0x200);
>              sysbus_init_mmio(sbd, &s->vifaceiomem[i + 1]);
>          }
>      }
> 


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[Qemu-devel] [PATCH 3/9] hw/arm/vexpress: Connect VIRQ and VFIQ

[Peter Maydell]

Connect the VIRQ and VFIQ lines from the GIC to the CPU;
these exist always for both CPU and GIC whether the
virtualization extensions are enabled or not, so we
can just unconditionally connect them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/vexpress.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index 5bfe2e43487..dc47ed84c20 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -251,6 +251,10 @@ static void init_cpus(const char *cpu_type, const char *privdev,
         sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
         sysbus_connect_irq(busdev, n + smp_cpus,
                            qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
+        sysbus_connect_irq(busdev, n + 2 * smp_cpus,
+                           qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
+        sysbus_connect_irq(busdev, n + 3 * smp_cpus,
+                           qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
     }
 }
 
-- 
2.18.0

Re: [Qemu-devel] [PATCH 3/9] hw/arm/vexpress: Connect VIRQ and VFIQ

[Luc Michel]

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On 8/21/18 3:28 PM, Peter Maydell wrote:
> Connect the VIRQ and VFIQ lines from the GIC to the CPU;
> these exist always for both CPU and GIC whether the
> virtualization extensions are enabled or not, so we
> can just unconditionally connect them.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

> ---
>  hw/arm/vexpress.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
> index 5bfe2e43487..dc47ed84c20 100644
> --- a/hw/arm/vexpress.c
> +++ b/hw/arm/vexpress.c
> @@ -251,6 +251,10 @@ static void init_cpus(const char *cpu_type, const char *privdev,
>          sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
>          sysbus_connect_irq(busdev, n + smp_cpus,
>                             qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
> +        sysbus_connect_irq(busdev, n + 2 * smp_cpus,
> +                           qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
> +        sysbus_connect_irq(busdev, n + 3 * smp_cpus,
> +                           qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
>      }
>  }
>  
> 


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[Qemu-devel] [PATCH 4/9] hw/arm/highbank: Connect VIRQ and VFIQ

[Peter Maydell]

Connect the VIRQ and VFIQ lines from the GIC to the CPU;
these exist always for both CPU and GIC whether the
virtualization extensions are enabled or not, so we
can just unconditionally connect them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/highbank.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index 6d42fce2c37..fb9efa02c35 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -243,6 +243,8 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
     int n;
     qemu_irq cpu_irq[4];
     qemu_irq cpu_fiq[4];
+    qemu_irq cpu_virq[4];
+    qemu_irq cpu_vfiq[4];
     MemoryRegion *sysram;
     MemoryRegion *dram;
     MemoryRegion *sysmem;
@@ -282,6 +284,8 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
         object_property_set_bool(cpuobj, true, "realized", &error_fatal);
         cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
         cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ);
+        cpu_virq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VIRQ);
+        cpu_vfiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VFIQ);
     }
 
     sysmem = get_system_memory();
@@ -329,6 +333,8 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
     for (n = 0; n < smp_cpus; n++) {
         sysbus_connect_irq(busdev, n, cpu_irq[n]);
         sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]);
+        sysbus_connect_irq(busdev, n + 2 * smp_cpus, cpu_virq[n]);
+        sysbus_connect_irq(busdev, n + 3 * smp_cpus, cpu_vfiq[n]);
     }
 
     for (n = 0; n < 128; n++) {
-- 
2.18.0

Re: [Qemu-devel] [PATCH 4/9] hw/arm/highbank: Connect VIRQ and VFIQ

[Luc Michel]

[-- Attachment #1: Type: text/plain, Size: 1892 bytes --]

On 8/21/18 3:28 PM, Peter Maydell wrote:
> Connect the VIRQ and VFIQ lines from the GIC to the CPU;
> these exist always for both CPU and GIC whether the
> virtualization extensions are enabled or not, so we
> can just unconditionally connect them.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

> ---
>  hw/arm/highbank.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
> index 6d42fce2c37..fb9efa02c35 100644
> --- a/hw/arm/highbank.c
> +++ b/hw/arm/highbank.c
> @@ -243,6 +243,8 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
>      int n;
>      qemu_irq cpu_irq[4];
>      qemu_irq cpu_fiq[4];
> +    qemu_irq cpu_virq[4];
> +    qemu_irq cpu_vfiq[4];
>      MemoryRegion *sysram;
>      MemoryRegion *dram;
>      MemoryRegion *sysmem;
> @@ -282,6 +284,8 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
>          object_property_set_bool(cpuobj, true, "realized", &error_fatal);
>          cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
>          cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ);
> +        cpu_virq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VIRQ);
> +        cpu_vfiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VFIQ);
>      }
>  
>      sysmem = get_system_memory();
> @@ -329,6 +333,8 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
>      for (n = 0; n < smp_cpus; n++) {
>          sysbus_connect_irq(busdev, n, cpu_irq[n]);
>          sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]);
> +        sysbus_connect_irq(busdev, n + 2 * smp_cpus, cpu_virq[n]);
> +        sysbus_connect_irq(busdev, n + 3 * smp_cpus, cpu_vfiq[n]);
>      }
>  
>      for (n = 0; n < 128; n++) {
> 


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[Qemu-devel] [PATCH 5/9] hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ

[Peter Maydell]

Connect the VIRQ and VFIQ lines from the GIC to the CPU;
these exist always for both CPU and GIC whether the
virtualization extensions are enabled or not, so we
can just unconditionally connect them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/fsl-imx6ul.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index 258f4706234..4b56bfa8d16 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -207,6 +207,10 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
         irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
         sysbus_connect_irq(sbd, i, irq);
         sysbus_connect_irq(sbd, i + smp_cpus, qdev_get_gpio_in(d, ARM_CPU_FIQ));
+        sysbus_connect_irq(sbd, i + 2 * smp_cpus,
+                           qdev_get_gpio_in(d, ARM_CPU_VIRQ));
+        sysbus_connect_irq(sbd, i + 3 * smp_cpus,
+                           qdev_get_gpio_in(d, ARM_CPU_VFIQ));
     }
 
     /*
-- 
2.18.0

Re: [Qemu-devel] [PATCH 5/9] hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ

[Luc Michel]

[-- Attachment #1: Type: text/plain, Size: 1157 bytes --]



On 8/21/18 3:28 PM, Peter Maydell wrote:
> Connect the VIRQ and VFIQ lines from the GIC to the CPU;
> these exist always for both CPU and GIC whether the
> virtualization extensions are enabled or not, so we
> can just unconditionally connect them.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

> ---
>  hw/arm/fsl-imx6ul.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
> index 258f4706234..4b56bfa8d16 100644
> --- a/hw/arm/fsl-imx6ul.c
> +++ b/hw/arm/fsl-imx6ul.c
> @@ -207,6 +207,10 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
>          irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
>          sysbus_connect_irq(sbd, i, irq);
>          sysbus_connect_irq(sbd, i + smp_cpus, qdev_get_gpio_in(d, ARM_CPU_FIQ));
> +        sysbus_connect_irq(sbd, i + 2 * smp_cpus,
> +                           qdev_get_gpio_in(d, ARM_CPU_VIRQ));
> +        sysbus_connect_irq(sbd, i + 3 * smp_cpus,
> +                           qdev_get_gpio_in(d, ARM_CPU_VFIQ));
>      }
>  
>      /*
> 


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[Qemu-devel] [PATCH 6/9] hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ

[Peter Maydell]

Connect the VIRQ and VFIQ lines from the GIC to the CPU;
these exist always for both CPU and GIC whether the
virtualization extensions are enabled or not, so we
can just unconditionally connect them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/fsl-imx7.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index d5e26855a55..7663ad68610 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -209,6 +209,10 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
         sysbus_connect_irq(sbd, i, irq);
         irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
         sysbus_connect_irq(sbd, i + smp_cpus, irq);
+        irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
+        sysbus_connect_irq(sbd, i + 2 * smp_cpus, irq);
+        irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
+        sysbus_connect_irq(sbd, i + 3 * smp_cpus, irq);
     }
 
     /*
-- 
2.18.0

Re: [Qemu-devel] [PATCH 6/9] hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ

[Luc Michel]

[-- Attachment #1: Type: text/plain, Size: 1100 bytes --]



On 8/21/18 3:28 PM, Peter Maydell wrote:
> Connect the VIRQ and VFIQ lines from the GIC to the CPU;
> these exist always for both CPU and GIC whether the
> virtualization extensions are enabled or not, so we
> can just unconditionally connect them.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

> ---
>  hw/arm/fsl-imx7.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
> index d5e26855a55..7663ad68610 100644
> --- a/hw/arm/fsl-imx7.c
> +++ b/hw/arm/fsl-imx7.c
> @@ -209,6 +209,10 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
>          sysbus_connect_irq(sbd, i, irq);
>          irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
>          sysbus_connect_irq(sbd, i + smp_cpus, irq);
> +        irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
> +        sysbus_connect_irq(sbd, i + 2 * smp_cpus, irq);
> +        irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
> +        sysbus_connect_irq(sbd, i + 3 * smp_cpus, irq);
>      }
>  
>      /*
> 


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[Qemu-devel] [PATCH 7/9] hw/cpu/a15mpcore: If CPU has EL2, enable it on the GIC and wire it up

[Peter Maydell]

For the A15MPCore internal peripheral object, we handle GIC
security extensions support by checking whether the CPUs
have EL3 enabled; if so then we enable it also on the GIC.
Handle the virtualization extensions in the same way: if the
CPU has EL2 then enable it on the GIC and wire up the
virtualization-specific memory regions and the maintenance
interrupt.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/cpu/a15mpcore.c | 31 ++++++++++++++++++++++++++++---
 1 file changed, 28 insertions(+), 3 deletions(-)

diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index 43c10794938..226ce8900f2 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -53,6 +53,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
     int i;
     Error *err = NULL;
     bool has_el3;
+    bool has_el2;
     Object *cpuobj;
 
     gicdev = DEVICE(&s->gic);
@@ -67,6 +68,10 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
         has_el3 = object_property_find(cpuobj, "has_el3", NULL) &&
             object_property_get_bool(cpuobj, "has_el3", &error_abort);
         qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
+        /* Similarly for virtualization support */
+        has_el2 = object_property_find(cpuobj, "has_el2", NULL) &&
+            object_property_get_bool(cpuobj, "has_el2", &error_abort);
+        qdev_prop_set_bit(gicdev, "has-virtualization-extensions", has_el2);
     }
 
     object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
@@ -103,20 +108,40 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
                                   qdev_get_gpio_in(gicdev,
                                                    ppibase + timer_irq[irq]));
         }
+        if (has_el2) {
+            /* Connect the GIC maintenance interrupt to PPI ID 25 */
+            sysbus_connect_irq(SYS_BUS_DEVICE(gicdev), i + 4 * s->num_cpu,
+                               qdev_get_gpio_in(gicdev, ppibase + 25));
+        }
     }
 
     /* Memory map (addresses are offsets from PERIPHBASE):
      *  0x0000-0x0fff -- reserved
      *  0x1000-0x1fff -- GIC Distributor
      *  0x2000-0x3fff -- GIC CPU interface
-     *  0x4000-0x4fff -- GIC virtual interface control (not modelled)
-     *  0x5000-0x5fff -- GIC virtual interface control (not modelled)
-     *  0x6000-0x7fff -- GIC virtual CPU interface (not modelled)
+     *  0x4000-0x4fff -- GIC virtual interface control for this CPU
+     *  0x5000-0x51ff -- GIC virtual interface control for CPU 0
+     *  0x5200-0x53ff -- GIC virtual interface control for CPU 1
+     *  0x5400-0x55ff -- GIC virtual interface control for CPU 2
+     *  0x5600-0x57ff -- GIC virtual interface control for CPU 3
+     *  0x6000-0x7fff -- GIC virtual CPU interface
      */
     memory_region_add_subregion(&s->container, 0x1000,
                                 sysbus_mmio_get_region(busdev, 0));
     memory_region_add_subregion(&s->container, 0x2000,
                                 sysbus_mmio_get_region(busdev, 1));
+    if (has_el2) {
+        memory_region_add_subregion(&s->container, 0x4000,
+                                    sysbus_mmio_get_region(busdev, 2));
+        memory_region_add_subregion(&s->container, 0x6000,
+                                    sysbus_mmio_get_region(busdev, 3));
+        for (i = 0; i < s->num_cpu; i++) {
+            hwaddr base = 0x5000 + i * 0x200;
+            MemoryRegion *mr = sysbus_mmio_get_region(busdev,
+                                                      4 + s->num_cpu + i);
+            memory_region_add_subregion(&s->container, base, mr);
+        }
+    }
 }
 
 static Property a15mp_priv_properties[] = {
-- 
2.18.0

Re: [Qemu-devel] [PATCH 7/9] hw/cpu/a15mpcore: If CPU has EL2, enable it on the GIC and wire it up

[Luc Michel]

[-- Attachment #1: Type: text/plain, Size: 4057 bytes --]



On 8/21/18 3:28 PM, Peter Maydell wrote:
> For the A15MPCore internal peripheral object, we handle GIC
> security extensions support by checking whether the CPUs
> have EL3 enabled; if so then we enable it also on the GIC.
> Handle the virtualization extensions in the same way: if the
> CPU has EL2 then enable it on the GIC and wire up the
> virtualization-specific memory regions and the maintenance
> interrupt.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

> ---
>  hw/cpu/a15mpcore.c | 31 ++++++++++++++++++++++++++++---
>  1 file changed, 28 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
> index 43c10794938..226ce8900f2 100644
> --- a/hw/cpu/a15mpcore.c
> +++ b/hw/cpu/a15mpcore.c
> @@ -53,6 +53,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
>      int i;
>      Error *err = NULL;
>      bool has_el3;
> +    bool has_el2;
>      Object *cpuobj;
>  
>      gicdev = DEVICE(&s->gic);
> @@ -67,6 +68,10 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
>          has_el3 = object_property_find(cpuobj, "has_el3", NULL) &&
>              object_property_get_bool(cpuobj, "has_el3", &error_abort);
>          qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
> +        /* Similarly for virtualization support */
> +        has_el2 = object_property_find(cpuobj, "has_el2", NULL) &&
> +            object_property_get_bool(cpuobj, "has_el2", &error_abort);
> +        qdev_prop_set_bit(gicdev, "has-virtualization-extensions", has_el2);
>      }
>  
>      object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
> @@ -103,20 +108,40 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
>                                    qdev_get_gpio_in(gicdev,
>                                                     ppibase + timer_irq[irq]));
>          }
> +        if (has_el2) {
> +            /* Connect the GIC maintenance interrupt to PPI ID 25 */
> +            sysbus_connect_irq(SYS_BUS_DEVICE(gicdev), i + 4 * s->num_cpu,
> +                               qdev_get_gpio_in(gicdev, ppibase + 25));
> +        }
>      }
>  
>      /* Memory map (addresses are offsets from PERIPHBASE):
>       *  0x0000-0x0fff -- reserved
>       *  0x1000-0x1fff -- GIC Distributor
>       *  0x2000-0x3fff -- GIC CPU interface
> -     *  0x4000-0x4fff -- GIC virtual interface control (not modelled)
> -     *  0x5000-0x5fff -- GIC virtual interface control (not modelled)
> -     *  0x6000-0x7fff -- GIC virtual CPU interface (not modelled)
> +     *  0x4000-0x4fff -- GIC virtual interface control for this CPU
> +     *  0x5000-0x51ff -- GIC virtual interface control for CPU 0
> +     *  0x5200-0x53ff -- GIC virtual interface control for CPU 1
> +     *  0x5400-0x55ff -- GIC virtual interface control for CPU 2
> +     *  0x5600-0x57ff -- GIC virtual interface control for CPU 3
> +     *  0x6000-0x7fff -- GIC virtual CPU interface
>       */
>      memory_region_add_subregion(&s->container, 0x1000,
>                                  sysbus_mmio_get_region(busdev, 0));
>      memory_region_add_subregion(&s->container, 0x2000,
>                                  sysbus_mmio_get_region(busdev, 1));
> +    if (has_el2) {
> +        memory_region_add_subregion(&s->container, 0x4000,
> +                                    sysbus_mmio_get_region(busdev, 2));
> +        memory_region_add_subregion(&s->container, 0x6000,
> +                                    sysbus_mmio_get_region(busdev, 3));
> +        for (i = 0; i < s->num_cpu; i++) {
> +            hwaddr base = 0x5000 + i * 0x200;
> +            MemoryRegion *mr = sysbus_mmio_get_region(busdev,
> +                                                      4 + s->num_cpu + i);
> +            memory_region_add_subregion(&s->container, base, mr);
> +        }
> +    }
>  }
>  
>  static Property a15mp_priv_properties[] = {
> 


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[Qemu-devel] [PATCH 8/9] hw/arm/vexpress: Don't set info->secure_boot if CPU doesn't have EL3

[Peter Maydell]

Don't request that the arm_load_kernel() code should boot in secure
state if the CPU doesn't have a secure state. Currently this
doesn't make a difference because the boot.c code only examines
the secure_boot flag in code guarded by an ARM_FEATURE_EL3 check,
but upcoming changes for supporting booting into Hyp mode will
change that.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/vexpress.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index dc47ed84c20..3631f4de3a4 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -705,8 +705,8 @@ static void vexpress_common_init(MachineState *machine)
     daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
     daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr;
     daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb;
-    /* Indicate that when booting Linux we should be in secure state */
-    daughterboard->bootinfo.secure_boot = true;
+    /* When booting Linux we should be in secure state if the CPU has one. */
+    daughterboard->bootinfo.secure_boot = vms->secure;
     arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo);
 }
 
-- 
2.18.0

Re: [Qemu-devel] [PATCH 8/9] hw/arm/vexpress: Don't set info->secure_boot if CPU doesn't have EL3

[Luc Michel]

[-- Attachment #1: Type: text/plain, Size: 1420 bytes --]



On 8/21/18 3:28 PM, Peter Maydell wrote:
> Don't request that the arm_load_kernel() code should boot in secure
> state if the CPU doesn't have a secure state. Currently this
> doesn't make a difference because the boot.c code only examines
> the secure_boot flag in code guarded by an ARM_FEATURE_EL3 check,
> but upcoming changes for supporting booting into Hyp mode will
> change that.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

> ---
>  hw/arm/vexpress.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
> index dc47ed84c20..3631f4de3a4 100644
> --- a/hw/arm/vexpress.c
> +++ b/hw/arm/vexpress.c
> @@ -705,8 +705,8 @@ static void vexpress_common_init(MachineState *machine)
>      daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
>      daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr;
>      daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb;
> -    /* Indicate that when booting Linux we should be in secure state */
> -    daughterboard->bootinfo.secure_boot = true;
> +    /* When booting Linux we should be in secure state if the CPU has one. */
> +    daughterboard->bootinfo.secure_boot = vms->secure;
>      arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo);
>  }
>  
> 


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[Qemu-devel] [PATCH 9/9] hw/arm/vexpress: Add "virtualization" property controlling presence of EL2

[Peter Maydell]

Add a "virtualization" property to the vexpress-a15 board,
controlling presence of EL2. As with EL3, we default to
enabling it, but the user can disable it if they have an
older guest which can't cope with it being present.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/vexpress.c | 56 ++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 53 insertions(+), 3 deletions(-)

diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index 3631f4de3a4..c02d18ee618 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -172,6 +172,7 @@ typedef struct {
 typedef struct {
     MachineState parent;
     bool secure;
+    bool virt;
 } VexpressMachineState;
 
 #define TYPE_VEXPRESS_MACHINE   "vexpress"
@@ -203,7 +204,7 @@ struct VEDBoardInfo {
 };
 
 static void init_cpus(const char *cpu_type, const char *privdev,
-                      hwaddr periphbase, qemu_irq *pic, bool secure)
+                      hwaddr periphbase, qemu_irq *pic, bool secure, bool virt)
 {
     DeviceState *dev;
     SysBusDevice *busdev;
@@ -216,6 +217,11 @@ static void init_cpus(const char *cpu_type, const char *privdev,
         if (!secure) {
             object_property_set_bool(cpuobj, false, "has_el3", NULL);
         }
+        if (!virt) {
+            if (object_property_find(cpuobj, "has_el2", NULL)) {
+                object_property_set_bool(cpuobj, false, "has_el2", NULL);
+            }
+        }
 
         if (object_property_find(cpuobj, "reset-cbar", NULL)) {
             object_property_set_int(cpuobj, periphbase,
@@ -289,7 +295,8 @@ static void a9_daughterboard_init(const VexpressMachineState *vms,
     memory_region_add_subregion(sysmem, 0x60000000, ram);
 
     /* 0x1e000000 A9MPCore (SCU) private memory region */
-    init_cpus(cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, vms->secure);
+    init_cpus(cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic,
+              vms->secure, vms->virt);
 
     /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
 
@@ -370,7 +377,8 @@ static void a15_daughterboard_init(const VexpressMachineState *vms,
     memory_region_add_subregion(sysmem, 0x80000000, ram);
 
     /* 0x2c000000 A15MPCore private memory region (GIC) */
-    init_cpus(cpu_type, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure);
+    init_cpus(cpu_type, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure,
+              vms->virt);
 
     /* A15 daughterboard peripherals: */
 
@@ -724,6 +732,20 @@ static void vexpress_set_secure(Object *obj, bool value, Error **errp)
     vms->secure = value;
 }
 
+static bool vexpress_get_virt(Object *obj, Error **errp)
+{
+    VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
+
+    return vms->virt;
+}
+
+static void vexpress_set_virt(Object *obj, bool value, Error **errp)
+{
+    VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
+
+    vms->virt = value;
+}
+
 static void vexpress_instance_init(Object *obj)
 {
     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
@@ -738,6 +760,32 @@ static void vexpress_instance_init(Object *obj)
                                     NULL);
 }
 
+static void vexpress_a15_instance_init(Object *obj)
+{
+    VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
+
+    /*
+     * For the vexpress-a15, EL2 is by default enabled if EL3 is,
+     * but can also be specifically set to on or off.
+     */
+    vms->virt = true;
+    object_property_add_bool(obj, "virtualization", vexpress_get_virt,
+                             vexpress_set_virt, NULL);
+    object_property_set_description(obj, "virtualization",
+                                    "Set on/off to enable/disable the ARM "
+                                    "Virtualization Extensions "
+                                    "(defaults to same as 'secure')",
+                                    NULL);
+}
+
+static void vexpress_a9_instance_init(Object *obj)
+{
+    VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
+
+    /* The A9 doesn't have the virt extensions */
+    vms->virt = false;
+}
+
 static void vexpress_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
@@ -784,12 +832,14 @@ static const TypeInfo vexpress_a9_info = {
     .name = TYPE_VEXPRESS_A9_MACHINE,
     .parent = TYPE_VEXPRESS_MACHINE,
     .class_init = vexpress_a9_class_init,
+    .instance_init = vexpress_a9_instance_init,
 };
 
 static const TypeInfo vexpress_a15_info = {
     .name = TYPE_VEXPRESS_A15_MACHINE,
     .parent = TYPE_VEXPRESS_MACHINE,
     .class_init = vexpress_a15_class_init,
+    .instance_init = vexpress_a15_instance_init,
 };
 
 static void vexpress_machine_init(void)
-- 
2.18.0

Re: [Qemu-devel] [PATCH 9/9] hw/arm/vexpress: Add "virtualization" property controlling presence of EL2

[Luc Michel]

[-- Attachment #1: Type: text/plain, Size: 5134 bytes --]



On 8/21/18 3:28 PM, Peter Maydell wrote:
> Add a "virtualization" property to the vexpress-a15 board,
> controlling presence of EL2. As with EL3, we default to
> enabling it, but the user can disable it if they have an
> older guest which can't cope with it being present.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

> ---
>  hw/arm/vexpress.c | 56 ++++++++++++++++++++++++++++++++++++++++++++---
>  1 file changed, 53 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
> index 3631f4de3a4..c02d18ee618 100644
> --- a/hw/arm/vexpress.c
> +++ b/hw/arm/vexpress.c
> @@ -172,6 +172,7 @@ typedef struct {
>  typedef struct {
>      MachineState parent;
>      bool secure;
> +    bool virt;
>  } VexpressMachineState;
>  
>  #define TYPE_VEXPRESS_MACHINE   "vexpress"
> @@ -203,7 +204,7 @@ struct VEDBoardInfo {
>  };
>  
>  static void init_cpus(const char *cpu_type, const char *privdev,
> -                      hwaddr periphbase, qemu_irq *pic, bool secure)
> +                      hwaddr periphbase, qemu_irq *pic, bool secure, bool virt)
>  {
>      DeviceState *dev;
>      SysBusDevice *busdev;
> @@ -216,6 +217,11 @@ static void init_cpus(const char *cpu_type, const char *privdev,
>          if (!secure) {
>              object_property_set_bool(cpuobj, false, "has_el3", NULL);
>          }
> +        if (!virt) {
> +            if (object_property_find(cpuobj, "has_el2", NULL)) {
> +                object_property_set_bool(cpuobj, false, "has_el2", NULL);
> +            }
> +        }
>  
>          if (object_property_find(cpuobj, "reset-cbar", NULL)) {
>              object_property_set_int(cpuobj, periphbase,
> @@ -289,7 +295,8 @@ static void a9_daughterboard_init(const VexpressMachineState *vms,
>      memory_region_add_subregion(sysmem, 0x60000000, ram);
>  
>      /* 0x1e000000 A9MPCore (SCU) private memory region */
> -    init_cpus(cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, vms->secure);
> +    init_cpus(cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic,
> +              vms->secure, vms->virt);
>  
>      /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
>  
> @@ -370,7 +377,8 @@ static void a15_daughterboard_init(const VexpressMachineState *vms,
>      memory_region_add_subregion(sysmem, 0x80000000, ram);
>  
>      /* 0x2c000000 A15MPCore private memory region (GIC) */
> -    init_cpus(cpu_type, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure);
> +    init_cpus(cpu_type, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure,
> +              vms->virt);
>  
>      /* A15 daughterboard peripherals: */
>  
> @@ -724,6 +732,20 @@ static void vexpress_set_secure(Object *obj, bool value, Error **errp)
>      vms->secure = value;
>  }
>  
> +static bool vexpress_get_virt(Object *obj, Error **errp)
> +{
> +    VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
> +
> +    return vms->virt;
> +}
> +
> +static void vexpress_set_virt(Object *obj, bool value, Error **errp)
> +{
> +    VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
> +
> +    vms->virt = value;
> +}
> +
>  static void vexpress_instance_init(Object *obj)
>  {
>      VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
> @@ -738,6 +760,32 @@ static void vexpress_instance_init(Object *obj)
>                                      NULL);
>  }
>  
> +static void vexpress_a15_instance_init(Object *obj)
> +{
> +    VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
> +
> +    /*
> +     * For the vexpress-a15, EL2 is by default enabled if EL3 is,
> +     * but can also be specifically set to on or off.
> +     */
> +    vms->virt = true;
> +    object_property_add_bool(obj, "virtualization", vexpress_get_virt,
> +                             vexpress_set_virt, NULL);
> +    object_property_set_description(obj, "virtualization",
> +                                    "Set on/off to enable/disable the ARM "
> +                                    "Virtualization Extensions "
> +                                    "(defaults to same as 'secure')",
> +                                    NULL);
> +}
> +
> +static void vexpress_a9_instance_init(Object *obj)
> +{
> +    VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
> +
> +    /* The A9 doesn't have the virt extensions */
> +    vms->virt = false;
> +}
> +
>  static void vexpress_class_init(ObjectClass *oc, void *data)
>  {
>      MachineClass *mc = MACHINE_CLASS(oc);
> @@ -784,12 +832,14 @@ static const TypeInfo vexpress_a9_info = {
>      .name = TYPE_VEXPRESS_A9_MACHINE,
>      .parent = TYPE_VEXPRESS_MACHINE,
>      .class_init = vexpress_a9_class_init,
> +    .instance_init = vexpress_a9_instance_init,
>  };
>  
>  static const TypeInfo vexpress_a15_info = {
>      .name = TYPE_VEXPRESS_A15_MACHINE,
>      .parent = TYPE_VEXPRESS_MACHINE,
>      .class_init = vexpress_a15_class_init,
> +    .instance_init = vexpress_a15_instance_init,
>  };
>  
>  static void vexpress_machine_init(void)
> 


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