From: David Hildenbrand <david@redhat.com>
To: qemu-s390x@nongnu.org
Cc: qemu-devel@nongnu.org, Richard Henderson <rth@twiddle.net>,
Alexander Graf <agraf@suse.de>, Cornelia Huck <cohuck@redhat.com>,
Thomas Huth <thuth@redhat.com>,
David Hildenbrand <david@redhat.com>
Subject: [Qemu-devel] [PATCH v1 2/8] s390x/tcg: store in the TB flags if AFP is enabled
Date: Wed, 22 Aug 2018 09:57:44 +0200 [thread overview]
Message-ID: <20180822075750.12399-3-david@redhat.com> (raw)
In-Reply-To: <20180822075750.12399-1-david@redhat.com>
We exit the TB when changing the control registers, so just like PSW
bits, this should always be consistent for a TB.
Using the PSW bit semantic makes things a lot easier compared to
manually defining the sapre, shifted bits.
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/cpu.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 5e50c3a303..8c2320e882 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -255,6 +255,7 @@ extern const struct VMStateDescription vmstate_s390_cpu;
/* PSW defines */
#undef PSW_MASK_PER
+#undef PSW_MASK_UNUSED_2
#undef PSW_MASK_DAT
#undef PSW_MASK_IO
#undef PSW_MASK_EXT
@@ -273,6 +274,7 @@ extern const struct VMStateDescription vmstate_s390_cpu;
#undef PSW_MASK_ESA_ADDR
#define PSW_MASK_PER 0x4000000000000000ULL
+#define PSW_MASK_UNUSED_2 0x2000000000000000ULL
#define PSW_MASK_DAT 0x0400000000000000ULL
#define PSW_MASK_IO 0x0200000000000000ULL
#define PSW_MASK_EXT 0x0100000000000000ULL
@@ -318,6 +320,9 @@ extern const struct VMStateDescription vmstate_s390_cpu;
#define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \
| FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
+/* we'll use some unused PSW positions to store CR flags in tb flags */
+#define FLAG_MASK_AFP (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT)
+
/* Control register 0 bits */
#define CR0_LOWPROT 0x0000000010000000ULL
#define CR0_SECONDARY 0x0000000004000000ULL
@@ -364,6 +369,9 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
*pc = env->psw.addr;
*cs_base = env->ex_value;
*flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
+ if (env->cregs[0] & CR0_AFP) {
+ *flags |= FLAG_MASK_AFP;
+ }
}
/* PER bits from control register 9 */
--
2.17.1
next prev parent reply other threads:[~2018-08-22 8:07 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-22 7:57 [Qemu-devel] [PATCH v1 0/8] s390x/tcg: instruction flags and AFP registers David Hildenbrand
2018-08-22 7:57 ` [Qemu-devel] [PATCH v1 1/8] s390x/tcg: factor out and fix DATA exception injection David Hildenbrand
2018-08-22 16:31 ` Richard Henderson
2018-08-22 16:52 ` David Hildenbrand
2018-08-22 17:26 ` David Hildenbrand
2018-08-24 8:39 ` David Hildenbrand
2018-08-22 7:57 ` David Hildenbrand [this message]
2018-08-22 16:41 ` [Qemu-devel] [PATCH v1 2/8] s390x/tcg: store in the TB flags if AFP is enabled Richard Henderson
2018-08-22 7:57 ` [Qemu-devel] [PATCH v1 3/8] s390x/tcg: support flags for instructions David Hildenbrand
2018-08-22 7:57 ` [Qemu-devel] [PATCH v1 4/8] s390x/tcg: add instruction flags for floating point instructions David Hildenbrand
2018-08-22 7:57 ` [Qemu-devel] [PATCH v1 5/8] s390x/tcg: check for AFP-register, BFP and DFP data exceptions David Hildenbrand
2018-08-22 7:57 ` [Qemu-devel] [PATCH v1 6/8] s390x/tcg: handle privileged instructions via flags David Hildenbrand
2018-08-22 7:57 ` [Qemu-devel] [PATCH v1 7/8] s390x/tcg: fix FP register pair checks David Hildenbrand
2018-08-22 7:57 ` [Qemu-devel] [PATCH v1 8/8] s390x/tcg: refactor specification checking David Hildenbrand
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