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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 39/52] hw/arm/mps2-tz: Instantiate SPI controllers
Date: Fri, 24 Aug 2018 10:33:30 +0100	[thread overview]
Message-ID: <20180824093343.11346-40-peter.maydell@linaro.org> (raw)
In-Reply-To: <20180824093343.11346-1-peter.maydell@linaro.org>

The SPI controllers in the MPS2 AN505 board are PL022s.
We have a model of the PL022, so create these devices.

We don't currently model the LCD controller that sits behind
one of the PL022s; the others are intended to control devices
that sit on the FPGA's general purpose SPI connector or
"shield" expansion connectors.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180820141116.9118-22-peter.maydell@linaro.org
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/arm/mps2-tz.c | 38 ++++++++++++++++++++++++++++++++------
 1 file changed, 32 insertions(+), 6 deletions(-)

diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index d810e51a1b4..cedf605e20e 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -48,6 +48,7 @@
 #include "hw/misc/tz-msc.h"
 #include "hw/arm/iotkit.h"
 #include "hw/dma/pl080.h"
+#include "hw/ssi/pl022.h"
 #include "hw/devices.h"
 #include "net/net.h"
 #include "hw/core/split-irq.h"
@@ -73,7 +74,7 @@ typedef struct {
     MPS2FPGAIO fpgaio;
     TZPPC ppc[5];
     TZMPC ssram_mpc[3];
-    UnimplementedDeviceState spi[5];
+    PL022State spi[5];
     UnimplementedDeviceState i2c[4];
     UnimplementedDeviceState i2s_audio;
     UnimplementedDeviceState gpio[4];
@@ -324,6 +325,31 @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque,
     return sysbus_mmio_get_region(s, 0);
 }
 
+static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque,
+                              const char *name, hwaddr size)
+{
+    /*
+     * The AN505 has five PL022 SPI controllers.
+     * One of these should have the LCD controller behind it; the others
+     * are connected only to the FPGA's "general purpose SPI connector"
+     * or "shield" expansion connectors.
+     * Note that if we do implement devices behind SPI, the chip select
+     * lines are set via the "MISC" register in the MPS2 FPGAIO device.
+     */
+    PL022State *spi = opaque;
+    int i = spi - &mms->spi[0];
+    DeviceState *iotkitdev = DEVICE(&mms->iotkit);
+    SysBusDevice *s;
+
+    sysbus_init_child_obj(OBJECT(mms), name, spi, sizeof(mms->spi[0]),
+                          TYPE_PL022);
+    object_property_set_bool(OBJECT(spi), true, "realized", &error_fatal);
+    s = SYS_BUS_DEVICE(spi);
+    sysbus_connect_irq(s, 0,
+                       qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 51 + i));
+    return sysbus_mmio_get_region(s, 0);
+}
+
 static void mps2tz_common_init(MachineState *machine)
 {
     MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine);
@@ -422,11 +448,11 @@ static void mps2tz_common_init(MachineState *machine)
         }, {
             .name = "apb_ppcexp1",
             .ports = {
-                { "spi0", make_unimp_dev, &mms->spi[0], 0x40205000, 0x1000 },
-                { "spi1", make_unimp_dev, &mms->spi[1], 0x40206000, 0x1000 },
-                { "spi2", make_unimp_dev, &mms->spi[2], 0x40209000, 0x1000 },
-                { "spi3", make_unimp_dev, &mms->spi[3], 0x4020a000, 0x1000 },
-                { "spi4", make_unimp_dev, &mms->spi[4], 0x4020b000, 0x1000 },
+                { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000 },
+                { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000 },
+                { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000 },
+                { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000 },
+                { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000 },
                 { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 },
                 { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 },
                 { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 },
-- 
2.18.0

  parent reply	other threads:[~2018-08-24  9:34 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-24  9:32 [Qemu-devel] [PULL 00/52] target-arm queue Peter Maydell
2018-08-24  9:32 ` [Qemu-devel] [PULL 01/52] softfloat: Add scaling int-to-float routines Peter Maydell
2018-08-24  9:32 ` [Qemu-devel] [PULL 02/52] softfloat: Add scaling float-to-int routines Peter Maydell
2018-08-24  9:32 ` [Qemu-devel] [PULL 03/52] target/arm: Use the int-to-float-scale softfloat routines Peter Maydell
2018-08-24  9:32 ` [Qemu-devel] [PULL 04/52] target/arm: Use the float-to-int-scale " Peter Maydell
2018-08-24  9:32 ` [Qemu-devel] [PULL 05/52] hw/intc/arm_gic: Make per-cpu GICH memory regions 0x200 bytes large Peter Maydell
2018-08-24  9:32 ` [Qemu-devel] [PULL 06/52] hw/arm/vexpress: Connect VIRQ and VFIQ Peter Maydell
2018-08-24  9:32 ` [Qemu-devel] [PULL 07/52] hw/arm/highbank: " Peter Maydell
2018-08-24  9:32 ` [Qemu-devel] [PULL 08/52] hw/arm/fsl-imx6ul: " Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 09/52] " Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 10/52] hw/cpu/a15mpcore: If CPU has EL2, enable it on the GIC and wire it up Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 11/52] hw/arm/vexpress: Don't set info->secure_boot if CPU doesn't have EL3 Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 12/52] hw/arm/vexpress: Add "virtualization" property controlling presence of EL2 Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 13/52] target/arm: Implement RAZ/WI HACTLR2 Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 14/52] target/arm: Implement AArch32 HCR and HCR2 Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 15/52] target/arm: Factor out code for taking an AArch32 exception Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 16/52] target/arm: Implement support for taking exceptions to Hyp mode Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 17/52] target/arm: Clear CPSR.IL and CPSR.J on 32-bit exception entry Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 18/52] hw/arm/boot: AArch32 kernels should be started in Hyp mode if available Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 19/52] hw/misc/mps2-fpgaio: Implement 1Hz and 100Hz counters Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 20/52] hw/misc/mps2-fpgaio: Implement PSCNTR and COUNTER Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 21/52] hw/timer/cmsdk-apb-dualtimer: Implement CMSDK dual timer module Peter Maydell
2018-09-09 20:34   ` Paolo Bonzini
2018-08-24  9:33 ` [Qemu-devel] [PULL 22/52] hw/arm/iotkit: Wire up the dualtimer Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 23/52] hw/arm/mps2: Wire up dual-timer in mps2-an385 and mps2-an511 Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 24/52] hw/arm/iotkit: Wire up the watchdogs Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 25/52] hw/arm/iotkit: Wire up the S32KTIMER Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 26/52] hw/misc/iotkit-sysctl: Implement IoTKit system control element Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 27/52] hw/misc/iotkit-sysinfo: Implement IoTKit system information block Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 28/52] hw/misc/iotkit: Wire up the sysctl and sysinfo register blocks Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 29/52] hw/misc/tz-msc: Model TrustZone Master Security Controller Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 30/52] hw/misc/iotkit-secctl: Wire up registers for controlling MSCs Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 31/52] hw/arm/iotkit: Wire up the lines for MSCs Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 32/52] hw/arm/mps2-tz: Create PL081s and MSCs Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 33/52] hw/ssi/pl022: Allow use as embedded-struct device Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 34/52] hw/ssi/pl022: Set up reset function in class init Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 35/52] hw/ssi/pl022: Don't directly call vmstate_register() Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 36/52] hw/ssi/pl022: Use DeviceState::realize rather than SysBusDevice::init Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 37/52] hw/ssi/pl022: Correct wrong value for PL022_INT_RT Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 38/52] hw/ssi/pl022: Correct wrong DMACR and ICR handling Peter Maydell
2018-08-24  9:33 ` Peter Maydell [this message]
2018-08-24  9:33 ` [Qemu-devel] [PULL 40/52] hw/arm/mps2-tz: Fix MPS2 SCC config register values Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 41/52] target/arm: Untabify translate.c Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 42/52] target/arm: Untabify iwmmxt_helper.c Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 43/52] target/arm: Remove a handful of stray tabs Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 44/52] hw/misc/bcm2835_fb: Move config fields to their own struct Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 45/52] hw/misc/bcm2835_property: Track fb settings using BCM2835FBConfig Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 46/52] hw/display/bcm2835_fb: Drop unused size and pitch fields Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 47/52] hw/display/bcm2835_fb: Reset resolution, etc correctly Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 48/52] hw/display/bcm2835_fb: Abstract out calculation of pitch, size Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 49/52] hw/display/bcm2835_fb: Fix handling of virtual framebuffer Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 50/52] hw/display/bcm2835_fb: Validate config settings Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 51/52] hw/display/bcm2835_fb: Validate bcm2835_fb_mbox_push() config Peter Maydell
2018-08-24  9:33 ` [Qemu-devel] [PULL 52/52] hw/arm/mps2: Fix ID register errors on AN511 and AN385 Peter Maydell

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