From: Craig Janeczek <jancraig@amazon.com>
To: qemu-devel@nongnu.org
Cc: amarkovic@wavecomp.com, aurelien@aurel32.net,
Craig Janeczek <jancraig@amazon.com>
Subject: [Qemu-devel] [PATCH v3 1/8] target/mips: Introduce MXU registers
Date: Tue, 28 Aug 2018 09:00:34 -0400 [thread overview]
Message-ID: <20180828130041.26445-2-jancraig@amazon.com> (raw)
In-Reply-To: <20180828130041.26445-1-jancraig@amazon.com>
Define and initialize the 16 MXU registers.
Signed-off-by: Craig Janeczek <jancraig@amazon.com>
---
v1
- NA
v2
- NA
v3
- Initial patch, split out from prior first patch
target/mips/cpu.h | 1 +
target/mips/translate.c | 16 ++++++++++++++++
2 files changed, 17 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 009202cf64..4b2948a2c8 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -170,6 +170,7 @@ struct TCState {
MSACSR_FS_MASK)
float_status msa_fp_status;
+ target_ulong mxu_gpr[16];
};
typedef struct CPUMIPSState CPUMIPSState;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index bdd880bb77..416488b383 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1398,6 +1398,9 @@ static TCGv_i32 fpu_fcr0, fpu_fcr31;
static TCGv_i64 fpu_f64[32];
static TCGv_i64 msa_wr_d[64];
+/* MXU registers */
+static TCGv mxu_gpr[16];
+
#include "exec/gen-icount.h"
#define gen_helper_0e0i(name, arg) do { \
@@ -1517,6 +1520,13 @@ static const char * const msaregnames[] = {
"w30.d0", "w30.d1", "w31.d0", "w31.d1",
};
+static const char * const mxuregnames[] = {
+ "XR1", "XR2", "XR3", "XR4", "XR5",
+ "XR6", "XR7", "XR8", "XR9", "XR10",
+ "XR11", "XR12", "XR13", "XR14", "XR15",
+ "XR16",
+};
+
#define LOG_DISAS(...) \
do { \
if (MIPS_DEBUG_DISAS) { \
@@ -20742,6 +20752,12 @@ void mips_tcg_init(void)
fpu_fcr31 = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUMIPSState, active_fpu.fcr31),
"fcr31");
+
+ for (i = 0; i < 16; i++)
+ mxu_gpr[i] = tcg_global_mem_new(cpu_env,
+ offsetof(CPUMIPSState,
+ active_tc.mxu_gpr[i]),
+ mxuregnames[i]);
}
#include "translate_init.inc.c"
--
2.18.0
next prev parent reply other threads:[~2018-08-28 13:01 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-28 13:00 [Qemu-devel] [PATCH v3 0/8] Add limited MXU instruction support Craig Janeczek
2018-08-28 13:00 ` Craig Janeczek [this message]
2018-08-28 14:49 ` [Qemu-devel] [PATCH v3 1/8] target/mips: Introduce MXU registers Aleksandar Markovic
2018-08-28 14:52 ` Janeczek, Craig
2018-08-28 13:00 ` [Qemu-devel] [PATCH v3 2/8] target/mips: Add all MXU opcodes Craig Janeczek
2018-08-28 15:07 ` Aleksandar Markovic
2018-08-28 15:13 ` Janeczek, Craig
2018-08-28 16:51 ` Aleksandar Markovic
2018-08-28 18:54 ` Janeczek, Craig
2018-08-28 19:35 ` Aleksandar Markovic
2018-08-28 20:22 ` Janeczek, Craig
2018-08-28 20:37 ` Aleksandar Markovic
2018-08-28 13:00 ` [Qemu-devel] [PATCH v3 3/8] target/mips: Add MXU instructions S32I2M and S32M2I Craig Janeczek
2018-08-28 14:43 ` Aleksandar Markovic
2018-08-28 14:50 ` Janeczek, Craig
2018-08-28 16:53 ` Aleksandar Markovic
2018-08-28 17:29 ` Janeczek, Craig
2018-08-28 18:17 ` Aleksandar Markovic
2018-08-28 13:00 ` [Qemu-devel] [PATCH v3 4/8] target/mips: Add MXU instruction S8LDD Craig Janeczek
2018-08-28 14:23 ` Aleksandar Markovic
2018-08-30 20:11 ` Richard Henderson
2018-08-28 13:00 ` [Qemu-devel] [PATCH v3 5/8] target/mips: Add MXU instruction D16MUL Craig Janeczek
2018-08-28 13:00 ` [Qemu-devel] [PATCH v3 6/8] target/mips: Add MXU instruction D16MAC Craig Janeczek
2018-08-28 14:10 ` Aleksandar Markovic
2018-08-28 13:00 ` [Qemu-devel] [PATCH v3 7/8] target/mips: Add MXU instructions Q8MUL and Q8MULSU Craig Janeczek
2018-08-28 13:00 ` [Qemu-devel] [PATCH v3 8/8] target/mips: Add MXU instructions S32LDD and S32LDDR Craig Janeczek
2018-08-29 16:42 ` [Qemu-devel] [PATCH v3 0/8] Add limited MXU instruction support Aleksandar Markovic
2018-08-30 12:40 ` Aleksandar Markovic
2018-08-30 13:27 ` Janeczek, Craig
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