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From: Craig Janeczek <jancraig@amazon.com>
To: qemu-devel@nongnu.org
Cc: amarkovic@wavecomp.com, aurelien@aurel32.net,
	Craig Janeczek <jancraig@amazon.com>
Subject: [Qemu-devel] [PATCH v4 3/9] target/mips: Split mips instruction handling
Date: Thu, 30 Aug 2018 15:30:13 -0400	[thread overview]
Message-ID: <20180830193019.20104-4-jancraig@amazon.com> (raw)
In-Reply-To: <20180830193019.20104-1-jancraig@amazon.com>

Splits the instruction handling switch statement from the original
legacy code.

Signed-off-by: Craig Janeczek <jancraig@amazon.com>
---
 v1
    - NA
 v2
    - NA
 v3
    - NA
 v4
    - Initial patch

 target/mips/mips-defs.h |  1 +
 target/mips/translate.c | 28 +++++++++++++++++++++++++++-
 2 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index d239069975..5a409757f0 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -50,6 +50,7 @@
 #define   ASE_SMARTMIPS 0x00400000
 #define   ASE_MICROMIPS 0x00800000
 #define   ASE_MSA       0x01000000
+#define   ASE_MXU       0x02000000
 
 /* Chip specific instructions. */
 #define		INSN_LOONGSON2E  0x20000000
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a598f45558..53d896ebf9 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -17855,6 +17855,28 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
     }
 }
 
+static void decode_opc_special2_mxu(CPUMIPSState *env, DisasContext *ctx)
+{
+    int rs, rt, rd;
+    uint32_t op1;
+
+    rs = (ctx->opcode >> 21) & 0x1f;
+    rt = (ctx->opcode >> 16) & 0x1f;
+    rd = (ctx->opcode >> 11) & 0x1f;
+
+    op1 = MASK_SPECIAL2(ctx->opcode);
+
+    switch (op1) {
+    case OPC_MUL:
+        gen_arith(ctx, op1, rd, rs, rt);
+        break;
+    default:            /* Invalid */
+        MIPS_INVAL("special2_mxu");
+        generate_exception_end(ctx, EXCP_RI);
+        break;
+    }
+}
+
 static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
 {
     int rs, rt, rd;
@@ -19836,7 +19858,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
         decode_opc_special(env, ctx);
         break;
     case OPC_SPECIAL2:
-        decode_opc_special2_legacy(env, ctx);
+        if (ctx->insn_flags & ASE_MXU) {
+            decode_opc_special2_mxu(env, ctx);
+        } else {
+            decode_opc_special2_legacy(env, ctx);
+        }
         break;
     case OPC_SPECIAL3:
         decode_opc_special3(env, ctx);
-- 
2.18.0

  parent reply	other threads:[~2018-08-30 19:45 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-30 19:30 [Qemu-devel] [PATCH v4 0/9] Add limited MXU instruction support Craig Janeczek
2018-08-30 19:30 ` [Qemu-devel] [PATCH v4 1/9] target/mips: Introduce MXU registers Craig Janeczek
2018-09-12 19:59   ` Richard Henderson
2018-08-30 19:30 ` [Qemu-devel] [PATCH v4 2/9] target/mips: Add all MXU opcodes Craig Janeczek
2018-08-31 18:59   ` Aleksandar Markovic
2018-09-04 14:47     ` Janeczek, Craig
2018-08-30 19:30 ` Craig Janeczek [this message]
2018-08-31 18:40   ` [Qemu-devel] [PATCH v4 3/9] target/mips: Split mips instruction handling Aleksandar Markovic
2018-09-04 14:44     ` Janeczek, Craig
2018-09-05 17:21       ` Aleksandar Markovic
2018-09-05 17:25         ` Aleksandar Markovic
2018-08-30 19:30 ` [Qemu-devel] [PATCH v4 4/9] target/mips: Add MXU instructions S32I2M and S32M2I Craig Janeczek
2018-09-12 20:08   ` Richard Henderson
2018-08-30 19:30 ` [Qemu-devel] [PATCH v4 5/9] target/mips: Add MXU instruction S8LDD Craig Janeczek
2018-08-31 13:39   ` Aleksandar Markovic
2018-09-12 20:20     ` Richard Henderson
2018-09-12 20:19   ` Richard Henderson
2018-08-30 19:30 ` [Qemu-devel] [PATCH v4 6/9] target/mips: Add MXU instruction D16MUL Craig Janeczek
2018-08-30 19:30 ` [Qemu-devel] [PATCH v4 7/9] target/mips: Add MXU instruction D16MAC Craig Janeczek
2018-08-30 19:30 ` [Qemu-devel] [PATCH v4 8/9] target/mips: Add MXU instructions Q8MUL and Q8MULSU Craig Janeczek
2018-08-30 19:30 ` [Qemu-devel] [PATCH v4 9/9] target/mips: Add MXU instructions S32LDD and S32LDDR Craig Janeczek
2018-09-05 13:36 ` [Qemu-devel] [PATCH v4 0/9] Add limited MXU instruction support Aleksandar Markovic
2018-09-11 12:27   ` Janeczek, Craig

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