From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46348) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvgqD-0003VX-Ge for qemu-devel@nongnu.org; Fri, 31 Aug 2018 06:39:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fvgq9-0002U0-GU for qemu-devel@nongnu.org; Fri, 31 Aug 2018 06:39:49 -0400 Received: from 4.mo173.mail-out.ovh.net ([46.105.34.219]:55875) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fvgq9-0002TJ-41 for qemu-devel@nongnu.org; Fri, 31 Aug 2018 06:39:45 -0400 Received: from player168.ha.ovh.net (unknown [10.109.160.251]) by mo173.mail-out.ovh.net (Postfix) with ESMTP id CFC70D39A8 for ; Fri, 31 Aug 2018 12:39:43 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 31 Aug 2018 12:38:16 +0200 Message-Id: <20180831103816.13479-10-clg@kaod.org> In-Reply-To: <20180831103816.13479-1-clg@kaod.org> References: <20180831103816.13479-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 09/11] aspeed/smc: add DMA calibration settings List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , Joel Stanley , Andrew Jeffery , Alistair Francis , Peter Crosthwaite , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= When doing calibration, the SPI clock rate in the CE0 Control Register and the read delay cycles in the Read Timing Compensation Register are replaced by bit[11:4] of the DMA Control Register. Signed-off-by: C=C3=A9dric Le Goater --- hw/ssi/aspeed_smc.c | 54 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 534faec4c111..983066f5ad1d 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -695,6 +695,56 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr= addr, unsigned int size) } } =20 +static uint8_t aspeed_smc_hclk_divisor(uint8_t hclk_mask) +{ + /* HCLK/1 .. HCLK/16 */ + const uint8_t hclk_divisors[] =3D { + 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 + }; + int i; + + for (i =3D 0; i < ARRAY_SIZE(hclk_divisors); i++) { + if (hclk_mask =3D=3D hclk_divisors[i]) { + return i + 1; + } + } + + qemu_log_mask(LOG_GUEST_ERROR, "invalid HCLK mask %x", hclk_mask); + return 0; +} + +/* + * When doing calibration, the SPI clock rate in the CE0 Control + * Register and the read delay cycles in the Read Timing + * Compensation Register are replaced by bit[11:4] of the DMA + * Control Register. + */ +static void aspeed_smc_dma_calibration(AspeedSMCState *s) +{ + uint8_t delay =3D + (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_M= ASK; + uint8_t hclk_mask =3D + (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MAS= K; + uint8_t hclk_div =3D aspeed_smc_hclk_divisor(hclk_mask); + uint32_t hclk_shift =3D (hclk_div - 1) << 2; + uint8_t cs; + + /* Only HCLK/1 - HCLK/5 have tunable delays */ + if (hclk_div && hclk_div < 6) { + s->regs[s->r_timings] &=3D ~(0xf << hclk_shift); + s->regs[s->r_timings] |=3D delay << hclk_shift; + } + + /* + * TODO: choose CS depending on the DMA address. This is not used + * on the field. + */ + cs =3D 0; + s->regs[s->r_ctrl0 + cs] &=3D + ~(CE_CTRL_CLOCK_FREQ_MASK << CE_CTRL_CLOCK_FREQ_SHIFT); + s->regs[s->r_ctrl0 + cs] |=3D CE_CTRL_CLOCK_FREQ(hclk_div); +} + /* * Accumulate the result of the reads to provide a checksum that will * be used to validate the read timing settings. @@ -709,6 +759,10 @@ static void aspeed_smc_dma_checksum(AspeedSMCState *= s) return; } =20 + if (s->regs[R_DMA_CTRL] & DMA_CTRL_CALIB) { + aspeed_smc_dma_calibration(s); + } + while (s->regs[R_DMA_LEN]) { cpu_physical_memory_read(s->regs[R_DMA_FLASH_ADDR], &data, 4); =20 --=20 2.17.1