From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54953) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fw6qS-0005sK-4p for qemu-devel@nongnu.org; Sat, 01 Sep 2018 10:25:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fw6oK-0005NO-GX for qemu-devel@nongnu.org; Sat, 01 Sep 2018 10:23:37 -0400 From: Eric Auger Date: Sat, 1 Sep 2018 16:22:56 +0200 Message-Id: <20180901142312.11662-5-eric.auger@redhat.com> In-Reply-To: <20180901142312.11662-1-eric.auger@redhat.com> References: <20180901142312.11662-1-eric.auger@redhat.com> Subject: [Qemu-devel] [RFC 04/20] memory: add IOMMU_ATTR_VFIO_NESTED IOMMU memory region attribute List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org Cc: alex.williamson@redhat.com, mst@redhat.com, cdall@kernel.org, jean-philippe.brucker@arm.com, peterx@redhat.com, yi.l.liu@intel.com We introduce a new IOMMU Memory Region attribute, IOMMU_ATTR_VFIO_NESTED which tells whether the virtual IOMMU requires physical nested stages for VFIO integration. Intel virtual IOMMU supports Caching Mode and does not require 2 stages at physical level. However virtual ARM SMMU does not implement such caching mode and requires to use physical stage 1 for VFIO integration. Signed-off-by: Eric Auger --- include/exec/memory.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/exec/memory.h b/include/exec/memory.h index eb4f2fb249..b6e59c139c 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -209,7 +209,8 @@ struct MemoryRegionOps { }; enum IOMMUMemoryRegionAttr { - IOMMU_ATTR_SPAPR_TCE_FD + IOMMU_ATTR_SPAPR_TCE_FD, + IOMMU_ATTR_VFIO_NESTED, }; /** -- 2.17.1