From: Peter Xu <peterx@redhat.com>
To: Brijesh Singh <brijesh.singh@amd.com>
Cc: qemu-devel@nongnu.org, Tom Lendacky <Thomas.Lendacky@amd.com>,
Eduardo Habkost <ehabkost@redhat.com>,
"Michael S. Tsirkin" <mst@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>,
Richard Henderson <rth@twiddle.net>
Subject: Re: [Qemu-devel] [PATCH 4/6] i386: acpi: add IVHD device entry for IOAPIC
Date: Thu, 13 Sep 2018 11:20:47 +0800 [thread overview]
Message-ID: <20180913032047.GD10763@xz-x1> (raw)
In-Reply-To: <4aae9c00-9db6-83a5-4f47-01141dc6d115@amd.com>
On Wed, Sep 12, 2018 at 02:11:10PM -0500, Brijesh Singh wrote:
>
>
> On 09/11/2018 11:35 PM, Peter Xu wrote:
> > On Tue, Sep 11, 2018 at 11:49:47AM -0500, Brijesh Singh wrote:
> > > When interrupt remapping is enabled, add a special IVHD device
> > > (type IOAPIC) -- which is typically PCI device 14:0.0. Linux IOMMU driver
> > > checks for this special device.
> > >
> > > Cc: "Michael S. Tsirkin" <mst@redhat.com>
> > > Cc: Paolo Bonzini <pbonzini@redhat.com>
> > > Cc: Richard Henderson <rth@twiddle.net>
> > > Cc: Eduardo Habkost <ehabkost@redhat.com>
> > > Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
> > > Cc: Tom Lendacky <Thomas.Lendacky@amd.com>
> > > Cc: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
> > > Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
> > > ---
> > > hw/i386/acpi-build.c | 20 +++++++++++++++++++-
> > > 1 file changed, 19 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> > > index e1ee8ae..5c2c638 100644
> > > --- a/hw/i386/acpi-build.c
> > > +++ b/hw/i386/acpi-build.c
> > > @@ -2519,6 +2519,7 @@ build_dmar_q35(GArray *table_data, BIOSLinker *linker)
> > > static void
> > > build_amd_iommu(GArray *table_data, BIOSLinker *linker)
> > > {
> > > + int ivhd_table_len = 28;
> > > int iommu_start = table_data->len;
> > > AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
> > > @@ -2540,8 +2541,16 @@ build_amd_iommu(GArray *table_data, BIOSLinker *linker)
> > > (1UL << 6) | /* PrefSup */
> > > (1UL << 7), /* PPRSup */
> > > 1);
> > > +
> > > + /*
> > > + * When interrupt remapping is enabled, we add a special IVHD device
> > > + * for type IO-APIC.
> > > + */
> > > + if (s->intr_enabled) {
> > > + ivhd_table_len += 8;
> > > + }
> > > /* IVHD length */
> > > - build_append_int_noprefix(table_data, 28, 2);
> > > + build_append_int_noprefix(table_data, ivhd_table_len, 2);
> > > /* DeviceID */
> > > build_append_int_noprefix(table_data, s->devid, 2);
> > > /* Capability offset */
> > > @@ -2565,6 +2574,15 @@ build_amd_iommu(GArray *table_data, BIOSLinker *linker)
> > > */
> > > build_append_int_noprefix(table_data, 0x0000001, 4);
> > > + /*
> > > + * When interrupt remapping is enabled, Linux IOMMU driver also checks
> > > + * for special IVHD device (type IO-APIC), which is typically presented
> > > + * as PCI device 14:00.0.
> > > + */
> > > + if (s->intr_enabled) {
> > > + build_append_int_noprefix(table_data, 0x0100a00000000048, 8);
> >
> > Some comments on the bit definition would be nicer, or "please refer
> > to Table 95 of AMD-Vi spec".
> >
> > Could I ask how come the 14:00.0? Is that in the spec somewhere?
> >
> > And since you explicitly mentioned Linux, then... would it work for
> > Windows too?
> >
>
> The PCI 14:00.0 is SouthBridge IOAPIC device. On bare metal the timer
> subsystem is connected to the SB IOAPIC. The IVRS table must contains
> the entry of SB IOAPIC otherwise Linux will not enable the IR mapping
> while parsing the IVRS.
>
> On bare meta system, IVRS will always have entry for SB IOAPIC. As per
> Windows is concerned, I am not sure if Windows support interrupt remap.
> If it does, adding the SB IOAPIC devid should not cause any problem
> to it because its always available on bare metal system.
>
> Here is linux commit
>
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059
Thanks for these information. Please feel free to add some of the
information into the comment, that might explain itself better. When
referring to commits, I would suggest just use "Please refer to Linux
commit xxx (xxx)" rather than the link though.
Regards,
--
Peter Xu
next prev parent reply other threads:[~2018-09-13 3:21 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-11 16:49 [Qemu-devel] [PATCH 0/6] x86_iommu/amd: add interrupt remap support Brijesh Singh
2018-09-11 16:49 ` [Qemu-devel] [PATCH 1/6] x86_iommu: move the kernel-irqchip check in common code Brijesh Singh
2018-09-12 3:45 ` Peter Xu
2018-09-11 16:49 ` [Qemu-devel] [PATCH 2/6] x86_iommu/amd: Prepare for interrupt remap support Brijesh Singh
2018-09-12 3:52 ` Peter Xu
2018-09-12 18:59 ` Brijesh Singh
2018-09-13 3:15 ` Peter Xu
2018-09-13 8:15 ` Suravee Suthikulpanit
2018-09-13 8:48 ` Peter Xu
2018-09-13 14:47 ` Paolo Bonzini
2018-09-11 16:49 ` [Qemu-devel] [PATCH 3/6] x86_iommu/amd: Add interrupt remap support when VAPIC is not enabled Brijesh Singh
2018-09-12 3:37 ` Peter Xu
2018-09-12 18:50 ` Brijesh Singh
2018-09-13 2:59 ` Peter Xu
2018-09-11 16:49 ` [Qemu-devel] [PATCH 4/6] i386: acpi: add IVHD device entry for IOAPIC Brijesh Singh
2018-09-12 4:35 ` Peter Xu
2018-09-12 19:11 ` Brijesh Singh
2018-09-13 3:20 ` Peter Xu [this message]
2018-09-12 16:35 ` Igor Mammedov
2018-09-12 19:24 ` Brijesh Singh
2018-09-13 18:18 ` Michael S. Tsirkin
2018-09-13 22:20 ` Brijesh Singh
2018-09-13 22:29 ` Michael S. Tsirkin
2018-09-11 16:49 ` [Qemu-devel] [PATCH 6/6] x86_iommu/amd: Enable Guest virtual APIC support Brijesh Singh
2018-09-12 4:52 ` Peter Xu
2018-09-12 21:14 ` Brijesh Singh
2018-09-13 8:36 ` Suravee Suthikulpanit
2018-09-13 11:44 ` Peter Xu
2018-09-13 7:13 ` Suravee Suthikulpanit
2018-09-12 16:38 ` Igor Mammedov
[not found] ` <1536684589-11718-6-git-send-email-brijesh.singh@amd.com>
2018-09-13 7:16 ` [Qemu-devel] [PATCH 5/6] x86_iommu/amd: Add interrupt remap support when VAPIC is enabled Suravee Suthikulpanit
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180913032047.GD10763@xz-x1 \
--to=peterx@redhat.com \
--cc=Suravee.Suthikulpanit@amd.com \
--cc=Thomas.Lendacky@amd.com \
--cc=brijesh.singh@amd.com \
--cc=ehabkost@redhat.com \
--cc=mst@redhat.com \
--cc=pbonzini@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=rth@twiddle.net \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).