From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PATCH 04/13] target/arm: Derive id_isar2 from features
Date: Sat, 15 Sep 2018 09:17:29 -0700 [thread overview]
Message-ID: <20180915161738.25257-5-richard.henderson@linaro.org> (raw)
In-Reply-To: <20180915161738.25257-1-richard.henderson@linaro.org>
??? The assertion does fire for the old cpus; they may be existing bugs.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.c | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index a477e722af..379d6a08a4 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -821,6 +821,40 @@ static uint32_t resolve_id_isar1(CPUARMState *env)
return ret;
}
+static uint32_t resolve_id_isar2(CPUARMState *env, uint32_t orig)
+{
+ uint32_t ret = 0;
+
+ /* LoadStore */
+ ret = deposit32(ret, 0, 4,
+ arm_feature(env, ARM_FEATURE_V8) ? 2 :
+ arm_feature(env, ARM_FEATURE_V5) ? 1 : 0);
+ /*
+ * MemHint -- v7mp has pldw (4), v7 has pli (3), but values 1 & 2
+ * mean the same thing, and there does not seem to be a way to tell
+ * them apart for v5 & v6.
+ */
+ ret |= orig & MAKE_64BIT_MASK(4, 4);
+ /* MultiAccessInt -- micro-architectural detail. */
+ ret |= orig & MAKE_64BIT_MASK(8, 4);
+ /* Mult -- note we don't support pre-armv4t. */
+ ret = deposit32(ret, 12, 4, arm_feature(env, ARM_FEATURE_THUMB2) ? 2 : 1);
+ /* MultS -- note we don't support pre-armv4t. */
+ ret = deposit32(ret, 16, 4,
+ arm_feature(env, ARM_FEATURE_V6) ? 3 :
+ arm_feature(env, ARM_FEATURE_V5) ? 2 : 1);
+ /* MultU -- note we don't support pre-armv4t. */
+ ret = deposit32(ret, 20, 4, arm_feature(env, ARM_FEATURE_V6) ? 2 : 1);
+ /* PSR_AR */
+ ret = deposit32(ret, 24, 4, arm_feature(env, ARM_FEATURE_M) ? 0 : 1);
+ /* Reversal */
+ ret = deposit32(ret, 28, 4,
+ arm_feature(env, ARM_FEATURE_THUMB2) ? 2 :
+ arm_feature(env, ARM_FEATURE_V6) ? 1 : 0);
+
+ return ret;
+}
+
static void resolve_id_regs(ARMCPU *cpu)
{
CPUARMState *env = &cpu->env;
@@ -833,6 +867,10 @@ static void resolve_id_regs(ARMCPU *cpu)
orig = cpu->id_isar1;
cpu->id_isar1 = resolve_id_isar1(env);
g_assert_cmphex(cpu->id_isar1, ==, orig);
+
+ orig = cpu->id_isar2;
+ cpu->id_isar2 = resolve_id_isar2(env, orig);
+ g_assert_cmphex(cpu->id_isar2, ==, orig);
}
static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
--
2.17.1
next prev parent reply other threads:[~2018-09-15 16:17 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-15 16:17 [Qemu-devel] [RFC PATCH 00/13] target/arm: Derive cpu id regs from features Richard Henderson
2018-09-15 16:17 ` [Qemu-devel] [PATCH 01/13] target/arm: Add ARM_FEATURE_SWP Richard Henderson
2018-09-16 1:32 ` Peter Maydell
2018-09-16 15:53 ` Richard Henderson
2018-09-16 16:54 ` Peter Maydell
2018-09-15 16:17 ` [Qemu-devel] [PATCH 02/13] target/arm: Derive id_isar0 from features Richard Henderson
2018-09-15 16:17 ` [Qemu-devel] [PATCH 03/13] target/arm: Derive id_isar1 " Richard Henderson
2018-09-15 16:17 ` Richard Henderson [this message]
2018-09-15 16:17 ` [Qemu-devel] [PATCH 05/13] target/arm: Derive id_isar3 " Richard Henderson
2018-09-15 16:17 ` [Qemu-devel] [PATCH 06/13] target/arm: Derive id_isar4 " Richard Henderson
2018-09-15 16:17 ` [Qemu-devel] [PATCH 07/13] target/arm: Derive id_isar5 and id_isar6 " Richard Henderson
2018-09-15 16:17 ` [Qemu-devel] [PATCH 08/13] target/arm: Derive id_pfr0 " Richard Henderson
2018-09-15 16:17 ` [Qemu-devel] [PATCH 09/13] target/arm: Derive id_pfr1 " Richard Henderson
2018-09-15 16:17 ` [Qemu-devel] [PATCH 10/13] target/arm: Derive id_aa64isar0 " Richard Henderson
2018-09-15 16:17 ` [Qemu-devel] [PATCH 11/13] target/arm: Derive id_aa64isar1 " Richard Henderson
2018-09-15 16:17 ` [Qemu-devel] [PATCH 12/13] target/arm: Derive id_aa64pfr0 " Richard Henderson
2018-09-15 16:17 ` [Qemu-devel] [PATCH 13/13] target/arm: Remove assertions from resolve_id_regs Richard Henderson
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