From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46709) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7Lmp-0005IS-Ia for qemu-devel@nongnu.org; Tue, 02 Oct 2018 10:36:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g7LdD-0004RB-JA for qemu-devel@nongnu.org; Tue, 02 Oct 2018 10:26:36 -0400 From: Damien Hedde Date: Tue, 2 Oct 2018 16:24:43 +0200 Message-Id: <20181002142443.30976-10-damien.hedde@greensocs.com> In-Reply-To: <20181002142443.30976-1-damien.hedde@greensocs.com> References: <20181002142443.30976-1-damien.hedde@greensocs.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v5 9/9] hw/arm/xilinx_zynq: connect uart clocks to slcr List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, pbonzini@redhat.com, peter.maydell@linaro.org, alistair@alistair23.me, saipava@xilinx.com, mark.burton@greensocs.com, luc.michel@greensocs.com, konrad@adacore.com, edgar.iglesias@xilinx.com, Damien Hedde Add the connection between the slcr's output clocks and the uarts inputs. Signed-off-by: Damien Hedde --- hw/arm/xilinx_zynq.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index f1496d2927..88f61c6a18 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -166,7 +166,7 @@ static void zynq_init(MachineState *machine) MemoryRegion *address_space_mem =3D get_system_memory(); MemoryRegion *ext_ram =3D g_new(MemoryRegion, 1); MemoryRegion *ocm_ram =3D g_new(MemoryRegion, 1); - DeviceState *dev; + DeviceState *dev, *slcr; SysBusDevice *busdev; qemu_irq pic[64]; int n; @@ -212,9 +212,10 @@ static void zynq_init(MachineState *machine) 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2= aa, 0); =20 - dev =3D qdev_create(NULL, "xilinx,zynq_slcr"); - qdev_init_nofail(dev); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000); + /* Create slcr, keep a pointer to connect clocks */ + slcr =3D qdev_create(NULL, "xilinx,zynq_slcr"); + qdev_init_nofail(slcr); + sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000); =20 dev =3D qdev_create(NULL, TYPE_A9MPCORE_PRIV); qdev_prop_set_uint32(dev, "num-cpu", 1); @@ -235,8 +236,12 @@ static void zynq_init(MachineState *machine) sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET])= ; sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET])= ; =20 - cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0)); - cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1)); + dev =3D cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial= _hd(0)); + qdev_connect_clock(dev, "busclk", slcr, "uart0_amba_clk", &error_abo= rt); + qdev_connect_clock(dev, "refclk", slcr, "uart0_ref_clk", &error_abor= t); + dev =3D cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial= _hd(1)); + qdev_connect_clock(dev, "busclk", slcr, "uart1_amba_clk", &error_abo= rt); + qdev_connect_clock(dev, "refclk", slcr, "uart1_ref_clk", &error_abor= t); =20 sysbus_create_varargs("cadence_ttc", 0xF8001000, pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], = NULL); --=20 2.19.0