* [Qemu-devel] [PATCH v2 1/4] exec: introduce tlb_init
2018-10-03 20:04 [Qemu-devel] [PATCH v2 0/4] per-TLB lock Emilio G. Cota
@ 2018-10-03 20:04 ` Emilio G. Cota
2018-10-04 11:08 ` Alex Bennée
2018-10-03 20:04 ` [Qemu-devel] [PATCH v2 2/4] cputlb: fix assert_cpu_is_self macro Emilio G. Cota
` (3 subsequent siblings)
4 siblings, 1 reply; 12+ messages in thread
From: Emilio G. Cota @ 2018-10-03 20:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Paolo Bonzini, Richard Henderson, Alex Bennée
Paves the way for the addition of a per-TLB lock.
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
include/exec/exec-all.h | 8 ++++++++
accel/tcg/cputlb.c | 4 ++++
exec.c | 1 +
3 files changed, 13 insertions(+)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 5f78125582..815e5b1e83 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -99,6 +99,11 @@ void cpu_address_space_init(CPUState *cpu, int asidx,
#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
/* cputlb.c */
+/**
+ * tlb_init - initialize a CPU's TLB
+ * @cpu: CPU whose TLB should be initialized
+ */
+void tlb_init(CPUState *cpu);
/**
* tlb_flush_page:
* @cpu: CPU whose TLB should be flushed
@@ -258,6 +263,9 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr,
void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
uintptr_t retaddr);
#else
+static inline void tlb_init(CPUState *cpu)
+{
+}
static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
{
}
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index f4702ce91f..502eea2850 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -73,6 +73,10 @@ QEMU_BUILD_BUG_ON(sizeof(target_ulong) > sizeof(run_on_cpu_data));
QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16);
#define ALL_MMUIDX_BITS ((1 << NB_MMU_MODES) - 1)
+void tlb_init(CPUState *cpu)
+{
+}
+
/* flush_all_helper: run fn across all cpus
*
* If the wait flag is set then the src cpu's helper will be queued as
diff --git a/exec.c b/exec.c
index d0821e69aa..4fd831ef06 100644
--- a/exec.c
+++ b/exec.c
@@ -965,6 +965,7 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
tcg_target_initialized = true;
cc->tcg_initialize();
}
+ tlb_init(cpu);
#ifndef CONFIG_USER_ONLY
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
--
2.17.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [Qemu-devel] [PATCH v2 1/4] exec: introduce tlb_init
2018-10-03 20:04 ` [Qemu-devel] [PATCH v2 1/4] exec: introduce tlb_init Emilio G. Cota
@ 2018-10-04 11:08 ` Alex Bennée
0 siblings, 0 replies; 12+ messages in thread
From: Alex Bennée @ 2018-10-04 11:08 UTC (permalink / raw)
To: Emilio G. Cota; +Cc: qemu-devel, Paolo Bonzini, Richard Henderson
Emilio G. Cota <cota@braap.org> writes:
> Paves the way for the addition of a per-TLB lock.
>
> Signed-off-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> include/exec/exec-all.h | 8 ++++++++
> accel/tcg/cputlb.c | 4 ++++
> exec.c | 1 +
> 3 files changed, 13 insertions(+)
>
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index 5f78125582..815e5b1e83 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -99,6 +99,11 @@ void cpu_address_space_init(CPUState *cpu, int asidx,
>
> #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
> /* cputlb.c */
> +/**
> + * tlb_init - initialize a CPU's TLB
> + * @cpu: CPU whose TLB should be initialized
> + */
> +void tlb_init(CPUState *cpu);
> /**
> * tlb_flush_page:
> * @cpu: CPU whose TLB should be flushed
> @@ -258,6 +263,9 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr,
> void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
> uintptr_t retaddr);
> #else
> +static inline void tlb_init(CPUState *cpu)
> +{
> +}
> static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
> {
> }
> diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
> index f4702ce91f..502eea2850 100644
> --- a/accel/tcg/cputlb.c
> +++ b/accel/tcg/cputlb.c
> @@ -73,6 +73,10 @@ QEMU_BUILD_BUG_ON(sizeof(target_ulong) > sizeof(run_on_cpu_data));
> QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16);
> #define ALL_MMUIDX_BITS ((1 << NB_MMU_MODES) - 1)
>
> +void tlb_init(CPUState *cpu)
> +{
> +}
> +
> /* flush_all_helper: run fn across all cpus
> *
> * If the wait flag is set then the src cpu's helper will be queued as
> diff --git a/exec.c b/exec.c
> index d0821e69aa..4fd831ef06 100644
> --- a/exec.c
> +++ b/exec.c
> @@ -965,6 +965,7 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
> tcg_target_initialized = true;
> cc->tcg_initialize();
> }
> + tlb_init(cpu);
>
> #ifndef CONFIG_USER_ONLY
> if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
--
Alex Bennée
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v2 2/4] cputlb: fix assert_cpu_is_self macro
2018-10-03 20:04 [Qemu-devel] [PATCH v2 0/4] per-TLB lock Emilio G. Cota
2018-10-03 20:04 ` [Qemu-devel] [PATCH v2 1/4] exec: introduce tlb_init Emilio G. Cota
@ 2018-10-03 20:04 ` Emilio G. Cota
2018-10-03 20:23 ` Richard Henderson
2018-10-04 10:16 ` Alex Bennée
2018-10-03 20:04 ` [Qemu-devel] [PATCH v2 3/4] cputlb: serialize tlb updates with env->tlb_lock Emilio G. Cota
` (2 subsequent siblings)
4 siblings, 2 replies; 12+ messages in thread
From: Emilio G. Cota @ 2018-10-03 20:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Paolo Bonzini, Richard Henderson, Alex Bennée
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
accel/tcg/cputlb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 502eea2850..f6b388c961 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -58,9 +58,9 @@
} \
} while (0)
-#define assert_cpu_is_self(this_cpu) do { \
+#define assert_cpu_is_self(cpu) do { \
if (DEBUG_TLB_GATE) { \
- g_assert(!cpu->created || qemu_cpu_is_self(cpu)); \
+ g_assert(!(cpu)->created || qemu_cpu_is_self(cpu)); \
} \
} while (0)
--
2.17.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [Qemu-devel] [PATCH v2 2/4] cputlb: fix assert_cpu_is_self macro
2018-10-03 20:04 ` [Qemu-devel] [PATCH v2 2/4] cputlb: fix assert_cpu_is_self macro Emilio G. Cota
@ 2018-10-03 20:23 ` Richard Henderson
2018-10-04 10:16 ` Alex Bennée
1 sibling, 0 replies; 12+ messages in thread
From: Richard Henderson @ 2018-10-03 20:23 UTC (permalink / raw)
To: Emilio G. Cota, qemu-devel
Cc: Paolo Bonzini, Alex Bennée, Richard Henderson
On 10/3/18 3:04 PM, Emilio G. Cota wrote:
> Signed-off-by: Emilio G. Cota <cota@braap.org>
> ---
> accel/tcg/cputlb.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Qemu-devel] [PATCH v2 2/4] cputlb: fix assert_cpu_is_self macro
2018-10-03 20:04 ` [Qemu-devel] [PATCH v2 2/4] cputlb: fix assert_cpu_is_self macro Emilio G. Cota
2018-10-03 20:23 ` Richard Henderson
@ 2018-10-04 10:16 ` Alex Bennée
1 sibling, 0 replies; 12+ messages in thread
From: Alex Bennée @ 2018-10-04 10:16 UTC (permalink / raw)
To: Emilio G. Cota; +Cc: qemu-devel, Paolo Bonzini, Richard Henderson
Emilio G. Cota <cota@braap.org> writes:
> Signed-off-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> accel/tcg/cputlb.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
> index 502eea2850..f6b388c961 100644
> --- a/accel/tcg/cputlb.c
> +++ b/accel/tcg/cputlb.c
> @@ -58,9 +58,9 @@
> } \
> } while (0)
>
> -#define assert_cpu_is_self(this_cpu) do { \
> +#define assert_cpu_is_self(cpu) do { \
> if (DEBUG_TLB_GATE) { \
> - g_assert(!cpu->created || qemu_cpu_is_self(cpu)); \
> + g_assert(!(cpu)->created || qemu_cpu_is_self(cpu)); \
> } \
> } while (0)
--
Alex Bennée
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v2 3/4] cputlb: serialize tlb updates with env->tlb_lock
2018-10-03 20:04 [Qemu-devel] [PATCH v2 0/4] per-TLB lock Emilio G. Cota
2018-10-03 20:04 ` [Qemu-devel] [PATCH v2 1/4] exec: introduce tlb_init Emilio G. Cota
2018-10-03 20:04 ` [Qemu-devel] [PATCH v2 2/4] cputlb: fix assert_cpu_is_self macro Emilio G. Cota
@ 2018-10-03 20:04 ` Emilio G. Cota
2018-10-04 11:07 ` Alex Bennée
2018-10-03 20:04 ` [Qemu-devel] [PATCH v2 4/4] cputlb: read CPUTLBEntry.addr_write atomically Emilio G. Cota
2018-10-04 20:15 ` [Qemu-devel] [PATCH v2 0/4] per-TLB lock Alex Bennée
4 siblings, 1 reply; 12+ messages in thread
From: Emilio G. Cota @ 2018-10-03 20:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Paolo Bonzini, Richard Henderson, Alex Bennée
Currently we rely on atomic operations for cross-CPU invalidations.
There are two cases that these atomics miss: cross-CPU invalidations
can race with either (1) vCPU threads flushing their TLB, which
happens via memset, or (2) vCPUs calling tlb_reset_dirty on their TLB,
which updates .addr_write with a regular store. This results in
undefined behaviour, since we're mixing regular and atomic ops
on concurrent accesses.
Fix it by using tlb_lock, a per-vCPU lock. All updaters of tlb_table
and the corresponding victim cache now hold the lock.
The readers that do not hold tlb_lock must use atomic reads when
reading .addr_write, since this field can be updated by other threads;
the conversion to atomic reads is done in the next patch.
Note that an alternative fix would be to expand the use of atomic ops.
However, in the case of TLB flushes this would have a huge performance
impact, since (1) TLB flushes can happen very frequently and (2) we
currently use a full memory barrier to flush each TLB entry, and a TLB
has many entries. Instead, acquiring the lock is barely slower than a
full memory barrier since it is uncontended, and with a single lock
acquisition we can flush the entire TLB.
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
include/exec/cpu-defs.h | 2 +
accel/tcg/cputlb.c | 153 ++++++++++++++++++++++------------------
2 files changed, 87 insertions(+), 68 deletions(-)
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index a171ffc1a4..bcc40c8ef5 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -142,6 +142,8 @@ typedef struct CPUIOTLBEntry {
#define CPU_COMMON_TLB \
/* The meaning of the MMU modes is defined in the target code. */ \
+ /* tlb_lock serializes updates to tlb_table and tlb_v_table */ \
+ QemuMutex tlb_lock; \
CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \
CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index f6b388c961..142a9cdf9e 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -75,6 +75,9 @@ QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16);
void tlb_init(CPUState *cpu)
{
+ CPUArchState *env = cpu->env_ptr;
+
+ qemu_mutex_init(&env->tlb_lock);
}
/* flush_all_helper: run fn across all cpus
@@ -129,8 +132,17 @@ static void tlb_flush_nocheck(CPUState *cpu)
atomic_set(&env->tlb_flush_count, env->tlb_flush_count + 1);
tlb_debug("(count: %zu)\n", tlb_flush_count());
+ /*
+ * tlb_table/tlb_v_table updates from any thread must hold tlb_lock.
+ * However, updates from the owner thread (as is the case here; see the
+ * above assert_cpu_is_self) do not need atomic_set because all reads
+ * that do not hold the lock are performed by the same owner thread.
+ */
+ qemu_mutex_lock(&env->tlb_lock);
memset(env->tlb_table, -1, sizeof(env->tlb_table));
memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table));
+ qemu_mutex_unlock(&env->tlb_lock);
+
cpu_tb_jmp_cache_clear(cpu);
env->vtlb_index = 0;
@@ -182,6 +194,7 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data)
tlb_debug("start: mmu_idx:0x%04lx\n", mmu_idx_bitmask);
+ qemu_mutex_lock(&env->tlb_lock);
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
if (test_bit(mmu_idx, &mmu_idx_bitmask)) {
@@ -191,6 +204,7 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data)
memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[0]));
}
}
+ qemu_mutex_unlock(&env->tlb_lock);
cpu_tb_jmp_cache_clear(cpu);
@@ -247,22 +261,36 @@ static inline bool tlb_hit_page_anyprot(CPUTLBEntry *tlb_entry,
tlb_hit_page(tlb_entry->addr_code, page);
}
-static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong page)
+/* Called with tlb_lock held */
+static inline void tlb_flush_entry_locked(CPUTLBEntry *tlb_entry,
+ target_ulong page)
{
if (tlb_hit_page_anyprot(tlb_entry, page)) {
memset(tlb_entry, -1, sizeof(*tlb_entry));
}
}
-static inline void tlb_flush_vtlb_page(CPUArchState *env, int mmu_idx,
- target_ulong page)
+/* Called with tlb_lock held */
+static inline void tlb_flush_vtlb_page_locked(CPUArchState *env, int mmu_idx,
+ target_ulong page)
{
int k;
+
+ assert_cpu_is_self(ENV_GET_CPU(env));
for (k = 0; k < CPU_VTLB_SIZE; k++) {
- tlb_flush_entry(&env->tlb_v_table[mmu_idx][k], page);
+ tlb_flush_entry_locked(&env->tlb_v_table[mmu_idx][k], page);
}
}
+static inline void tlb_flush_vtlb_page(CPUArchState *env, int mmu_idx,
+ target_ulong page)
+{
+ assert_cpu_is_self(ENV_GET_CPU(env));
+ qemu_mutex_lock(&env->tlb_lock);
+ tlb_flush_vtlb_page_locked(env, mmu_idx, page);
+ qemu_mutex_unlock(&env->tlb_lock);
+}
+
static void tlb_flush_page_async_work(CPUState *cpu, run_on_cpu_data data)
{
CPUArchState *env = cpu->env_ptr;
@@ -286,10 +314,12 @@ static void tlb_flush_page_async_work(CPUState *cpu, run_on_cpu_data data)
addr &= TARGET_PAGE_MASK;
i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
+ qemu_mutex_lock(&env->tlb_lock);
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
- tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
- tlb_flush_vtlb_page(env, mmu_idx, addr);
+ tlb_flush_entry_locked(&env->tlb_table[mmu_idx][i], addr);
+ tlb_flush_vtlb_page_locked(env, mmu_idx, addr);
}
+ qemu_mutex_unlock(&env->tlb_lock);
tb_flush_jmp_cache(cpu, addr);
}
@@ -326,12 +356,14 @@ static void tlb_flush_page_by_mmuidx_async_work(CPUState *cpu,
tlb_debug("page:%d addr:"TARGET_FMT_lx" mmu_idx:0x%lx\n",
page, addr, mmu_idx_bitmap);
+ qemu_mutex_lock(&env->tlb_lock);
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
if (test_bit(mmu_idx, &mmu_idx_bitmap)) {
- tlb_flush_entry(&env->tlb_table[mmu_idx][page], addr);
- tlb_flush_vtlb_page(env, mmu_idx, addr);
+ tlb_flush_entry_locked(&env->tlb_table[mmu_idx][page], addr);
+ tlb_flush_vtlb_page_locked(env, mmu_idx, addr);
}
}
+ qemu_mutex_unlock(&env->tlb_lock);
tb_flush_jmp_cache(cpu, addr);
}
@@ -454,72 +486,49 @@ void tlb_unprotect_code(ram_addr_t ram_addr)
* most usual is detecting writes to code regions which may invalidate
* generated code.
*
- * Because we want other vCPUs to respond to changes straight away we
- * update the te->addr_write field atomically. If the TLB entry has
- * been changed by the vCPU in the mean time we skip the update.
+ * Other vCPUs might be reading their TLBs during guest execution, so we update
+ * te->addr_write with atomic_set. We don't need to worry about this for
+ * oversized guests as MTTCG is disabled for them.
*
- * As this function uses atomic accesses we also need to ensure
- * updates to tlb_entries follow the same access rules. We don't need
- * to worry about this for oversized guests as MTTCG is disabled for
- * them.
+ * Called with tlb_lock held.
*/
-
-static void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start,
- uintptr_t length)
+static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry,
+ uintptr_t start, uintptr_t length)
{
-#if TCG_OVERSIZED_GUEST
uintptr_t addr = tlb_entry->addr_write;
if ((addr & (TLB_INVALID_MASK | TLB_MMIO | TLB_NOTDIRTY)) == 0) {
addr &= TARGET_PAGE_MASK;
addr += tlb_entry->addend;
if ((addr - start) < length) {
+#if TCG_OVERSIZED_GUEST
tlb_entry->addr_write |= TLB_NOTDIRTY;
- }
- }
#else
- /* paired with atomic_mb_set in tlb_set_page_with_attrs */
- uintptr_t orig_addr = atomic_mb_read(&tlb_entry->addr_write);
- uintptr_t addr = orig_addr;
-
- if ((addr & (TLB_INVALID_MASK | TLB_MMIO | TLB_NOTDIRTY)) == 0) {
- addr &= TARGET_PAGE_MASK;
- addr += atomic_read(&tlb_entry->addend);
- if ((addr - start) < length) {
- uintptr_t notdirty_addr = orig_addr | TLB_NOTDIRTY;
- atomic_cmpxchg(&tlb_entry->addr_write, orig_addr, notdirty_addr);
+ atomic_set(&tlb_entry->addr_write,
+ tlb_entry->addr_write | TLB_NOTDIRTY);
+#endif
}
}
-#endif
}
-/* For atomic correctness when running MTTCG we need to use the right
- * primitives when copying entries */
-static inline void copy_tlb_helper(CPUTLBEntry *d, CPUTLBEntry *s,
- bool atomic_set)
+/* Called with tlb_lock held */
+static void copy_tlb_helper_locked(CPUTLBEntry *d, const CPUTLBEntry *s)
{
-#if TCG_OVERSIZED_GUEST
*d = *s;
-#else
- if (atomic_set) {
- d->addr_read = s->addr_read;
- d->addr_code = s->addr_code;
- atomic_set(&d->addend, atomic_read(&s->addend));
- /* Pairs with flag setting in tlb_reset_dirty_range */
- atomic_mb_set(&d->addr_write, atomic_read(&s->addr_write));
- } else {
- d->addr_read = s->addr_read;
- d->addr_write = atomic_read(&s->addr_write);
- d->addr_code = s->addr_code;
- d->addend = atomic_read(&s->addend);
- }
-#endif
+}
+
+static void copy_tlb_helper(CPUArchState *env, CPUTLBEntry *d, CPUTLBEntry *s)
+{
+ assert_cpu_is_self(ENV_GET_CPU(env));
+ qemu_mutex_lock(&env->tlb_lock);
+ copy_tlb_helper_locked(d, s);
+ qemu_mutex_unlock(&env->tlb_lock);
}
/* This is a cross vCPU call (i.e. another vCPU resetting the flags of
- * the target vCPU). As such care needs to be taken that we don't
- * dangerously race with another vCPU update. The only thing actually
- * updated is the target TLB entry ->addr_write flags.
+ * the target vCPU).
+ * We must take tlb_lock to avoid racing with another vCPU update. The only
+ * thing actually updated is the target TLB entry ->addr_write flags.
*/
void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length)
{
@@ -528,22 +537,26 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length)
int mmu_idx;
env = cpu->env_ptr;
+ qemu_mutex_lock(&env->tlb_lock);
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
unsigned int i;
for (i = 0; i < CPU_TLB_SIZE; i++) {
- tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i],
- start1, length);
+ tlb_reset_dirty_range_locked(&env->tlb_table[mmu_idx][i], start1,
+ length);
}
for (i = 0; i < CPU_VTLB_SIZE; i++) {
- tlb_reset_dirty_range(&env->tlb_v_table[mmu_idx][i],
- start1, length);
+ tlb_reset_dirty_range_locked(&env->tlb_v_table[mmu_idx][i], start1,
+ length);
}
}
+ qemu_mutex_unlock(&env->tlb_lock);
}
-static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
+/* Called with tlb_lock held */
+static inline void tlb_set_dirty1_locked(CPUTLBEntry *tlb_entry,
+ target_ulong vaddr)
{
if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) {
tlb_entry->addr_write = vaddr;
@@ -562,16 +575,18 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr)
vaddr &= TARGET_PAGE_MASK;
i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
+ qemu_mutex_lock(&env->tlb_lock);
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
- tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr);
+ tlb_set_dirty1_locked(&env->tlb_table[mmu_idx][i], vaddr);
}
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
int k;
for (k = 0; k < CPU_VTLB_SIZE; k++) {
- tlb_set_dirty1(&env->tlb_v_table[mmu_idx][k], vaddr);
+ tlb_set_dirty1_locked(&env->tlb_v_table[mmu_idx][k], vaddr);
}
}
+ qemu_mutex_unlock(&env->tlb_lock);
}
/* Our TLB does not support large pages, so remember the area covered by
@@ -677,7 +692,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
CPUTLBEntry *tv = &env->tlb_v_table[mmu_idx][vidx];
/* Evict the old entry into the victim tlb. */
- copy_tlb_helper(tv, te, true);
+ copy_tlb_helper(env, tv, te);
env->iotlb_v[mmu_idx][vidx] = env->iotlb[mmu_idx][index];
}
@@ -729,9 +744,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
}
}
- /* Pairs with flag setting in tlb_reset_dirty_range */
- copy_tlb_helper(te, &tn, true);
- /* atomic_mb_set(&te->addr_write, write_address); */
+ copy_tlb_helper(env, te, &tn);
}
/* Add a new TLB entry, but without specifying the memory
@@ -895,6 +908,8 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index,
size_t elt_ofs, target_ulong page)
{
size_t vidx;
+
+ assert_cpu_is_self(ENV_GET_CPU(env));
for (vidx = 0; vidx < CPU_VTLB_SIZE; ++vidx) {
CPUTLBEntry *vtlb = &env->tlb_v_table[mmu_idx][vidx];
target_ulong cmp = *(target_ulong *)((uintptr_t)vtlb + elt_ofs);
@@ -903,9 +918,11 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index,
/* Found entry in victim tlb, swap tlb and iotlb. */
CPUTLBEntry tmptlb, *tlb = &env->tlb_table[mmu_idx][index];
- copy_tlb_helper(&tmptlb, tlb, false);
- copy_tlb_helper(tlb, vtlb, true);
- copy_tlb_helper(vtlb, &tmptlb, true);
+ qemu_mutex_lock(&env->tlb_lock);
+ copy_tlb_helper_locked(&tmptlb, tlb);
+ copy_tlb_helper_locked(tlb, vtlb);
+ copy_tlb_helper_locked(vtlb, &tmptlb);
+ qemu_mutex_unlock(&env->tlb_lock);
CPUIOTLBEntry tmpio, *io = &env->iotlb[mmu_idx][index];
CPUIOTLBEntry *vio = &env->iotlb_v[mmu_idx][vidx];
--
2.17.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [Qemu-devel] [PATCH v2 3/4] cputlb: serialize tlb updates with env->tlb_lock
2018-10-03 20:04 ` [Qemu-devel] [PATCH v2 3/4] cputlb: serialize tlb updates with env->tlb_lock Emilio G. Cota
@ 2018-10-04 11:07 ` Alex Bennée
0 siblings, 0 replies; 12+ messages in thread
From: Alex Bennée @ 2018-10-04 11:07 UTC (permalink / raw)
To: Emilio G. Cota; +Cc: qemu-devel, Paolo Bonzini, Richard Henderson
Emilio G. Cota <cota@braap.org> writes:
> Currently we rely on atomic operations for cross-CPU invalidations.
> There are two cases that these atomics miss: cross-CPU invalidations
> can race with either (1) vCPU threads flushing their TLB, which
> happens via memset, or (2) vCPUs calling tlb_reset_dirty on their TLB,
> which updates .addr_write with a regular store. This results in
> undefined behaviour, since we're mixing regular and atomic ops
> on concurrent accesses.
>
> Fix it by using tlb_lock, a per-vCPU lock. All updaters of tlb_table
> and the corresponding victim cache now hold the lock.
> The readers that do not hold tlb_lock must use atomic reads when
> reading .addr_write, since this field can be updated by other threads;
> the conversion to atomic reads is done in the next patch.
>
> Note that an alternative fix would be to expand the use of atomic ops.
> However, in the case of TLB flushes this would have a huge performance
> impact, since (1) TLB flushes can happen very frequently and (2) we
> currently use a full memory barrier to flush each TLB entry, and a TLB
> has many entries. Instead, acquiring the lock is barely slower than a
> full memory barrier since it is uncontended, and with a single lock
> acquisition we can flush the entire TLB.
>
> Signed-off-by: Emilio G. Cota <cota@braap.org>
> ---
> include/exec/cpu-defs.h | 2 +
> accel/tcg/cputlb.c | 153 ++++++++++++++++++++++------------------
> 2 files changed, 87 insertions(+), 68 deletions(-)
>
> diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
> index a171ffc1a4..bcc40c8ef5 100644
> --- a/include/exec/cpu-defs.h
> +++ b/include/exec/cpu-defs.h
> @@ -142,6 +142,8 @@ typedef struct CPUIOTLBEntry {
>
> #define CPU_COMMON_TLB \
> /* The meaning of the MMU modes is defined in the target code. */ \
> + /* tlb_lock serializes updates to tlb_table and tlb_v_table */ \
> + QemuMutex tlb_lock;
> \
This fails to build on some targets due to a missing typedef - not sure
why the include chain is different:
CC moxie-softmmu/exec.o
In file included from /home/alex/lsrc/qemu/qemu.git/target/moxie/cpu.h:36:0,
from /home/alex/lsrc/qemu/qemu.git/exec.c:23:
/home/alex/lsrc/qemu/qemu.git/include/exec/cpu-defs.h:146:15: error: field ‘tlb_lock’ has incomplete type
QemuMutex tlb_lock; \
^
/home/alex/lsrc/qemu/qemu.git/include/exec/cpu-defs.h:165:5: note: in expansion of macro ‘CPU_COMMON_TLB’
CPU_COMMON_TLB \
^~~~~~~~~~~~~~
/home/alex/lsrc/qemu/qemu.git/target/moxie/cpu.h:61:5: note: in expansion of macro ‘CPU_COMMON’
CPU_COMMON
^~~~~~~~~~
/home/alex/lsrc/qemu/qemu.git/rules.mak:69: recipe for target 'exec.o' failed
make[1]: *** [exec.o] Error 1
Makefile:483: recipe for target 'subdir-moxie-softmmu' failed
make: *** [subdir-moxie-softmmu] Error 2
make: *** Waiting for unfinished jobs....
> CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
> CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \
> CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
> diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
> index f6b388c961..142a9cdf9e 100644
> --- a/accel/tcg/cputlb.c
> +++ b/accel/tcg/cputlb.c
> @@ -75,6 +75,9 @@ QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16);
>
> void tlb_init(CPUState *cpu)
> {
> + CPUArchState *env = cpu->env_ptr;
> +
> + qemu_mutex_init(&env->tlb_lock);
> }
>
> /* flush_all_helper: run fn across all cpus
> @@ -129,8 +132,17 @@ static void tlb_flush_nocheck(CPUState *cpu)
> atomic_set(&env->tlb_flush_count, env->tlb_flush_count + 1);
> tlb_debug("(count: %zu)\n", tlb_flush_count());
>
> + /*
> + * tlb_table/tlb_v_table updates from any thread must hold tlb_lock.
> + * However, updates from the owner thread (as is the case here; see the
> + * above assert_cpu_is_self) do not need atomic_set because all reads
> + * that do not hold the lock are performed by the same owner thread.
> + */
> + qemu_mutex_lock(&env->tlb_lock);
> memset(env->tlb_table, -1, sizeof(env->tlb_table));
> memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table));
> + qemu_mutex_unlock(&env->tlb_lock);
> +
> cpu_tb_jmp_cache_clear(cpu);
>
> env->vtlb_index = 0;
> @@ -182,6 +194,7 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data)
>
> tlb_debug("start: mmu_idx:0x%04lx\n", mmu_idx_bitmask);
>
> + qemu_mutex_lock(&env->tlb_lock);
> for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
>
> if (test_bit(mmu_idx, &mmu_idx_bitmask)) {
> @@ -191,6 +204,7 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data)
> memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[0]));
> }
> }
> + qemu_mutex_unlock(&env->tlb_lock);
>
> cpu_tb_jmp_cache_clear(cpu);
>
> @@ -247,22 +261,36 @@ static inline bool tlb_hit_page_anyprot(CPUTLBEntry *tlb_entry,
> tlb_hit_page(tlb_entry->addr_code, page);
> }
>
> -static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong page)
> +/* Called with tlb_lock held */
> +static inline void tlb_flush_entry_locked(CPUTLBEntry *tlb_entry,
> + target_ulong page)
> {
> if (tlb_hit_page_anyprot(tlb_entry, page)) {
> memset(tlb_entry, -1, sizeof(*tlb_entry));
> }
> }
>
> -static inline void tlb_flush_vtlb_page(CPUArchState *env, int mmu_idx,
> - target_ulong page)
> +/* Called with tlb_lock held */
> +static inline void tlb_flush_vtlb_page_locked(CPUArchState *env, int mmu_idx,
> + target_ulong page)
> {
> int k;
> +
> + assert_cpu_is_self(ENV_GET_CPU(env));
> for (k = 0; k < CPU_VTLB_SIZE; k++) {
> - tlb_flush_entry(&env->tlb_v_table[mmu_idx][k], page);
> + tlb_flush_entry_locked(&env->tlb_v_table[mmu_idx][k], page);
> }
> }
>
> +static inline void tlb_flush_vtlb_page(CPUArchState *env, int mmu_idx,
> + target_ulong page)
> +{
> + assert_cpu_is_self(ENV_GET_CPU(env));
> + qemu_mutex_lock(&env->tlb_lock);
> + tlb_flush_vtlb_page_locked(env, mmu_idx, page);
> + qemu_mutex_unlock(&env->tlb_lock);
> +}
> +
> static void tlb_flush_page_async_work(CPUState *cpu, run_on_cpu_data data)
> {
> CPUArchState *env = cpu->env_ptr;
> @@ -286,10 +314,12 @@ static void tlb_flush_page_async_work(CPUState *cpu, run_on_cpu_data data)
>
> addr &= TARGET_PAGE_MASK;
> i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
> + qemu_mutex_lock(&env->tlb_lock);
> for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
> - tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
> - tlb_flush_vtlb_page(env, mmu_idx, addr);
> + tlb_flush_entry_locked(&env->tlb_table[mmu_idx][i], addr);
> + tlb_flush_vtlb_page_locked(env, mmu_idx, addr);
> }
> + qemu_mutex_unlock(&env->tlb_lock);
>
> tb_flush_jmp_cache(cpu, addr);
> }
> @@ -326,12 +356,14 @@ static void tlb_flush_page_by_mmuidx_async_work(CPUState *cpu,
> tlb_debug("page:%d addr:"TARGET_FMT_lx" mmu_idx:0x%lx\n",
> page, addr, mmu_idx_bitmap);
>
> + qemu_mutex_lock(&env->tlb_lock);
> for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
> if (test_bit(mmu_idx, &mmu_idx_bitmap)) {
> - tlb_flush_entry(&env->tlb_table[mmu_idx][page], addr);
> - tlb_flush_vtlb_page(env, mmu_idx, addr);
> + tlb_flush_entry_locked(&env->tlb_table[mmu_idx][page], addr);
> + tlb_flush_vtlb_page_locked(env, mmu_idx, addr);
> }
> }
> + qemu_mutex_unlock(&env->tlb_lock);
>
> tb_flush_jmp_cache(cpu, addr);
> }
> @@ -454,72 +486,49 @@ void tlb_unprotect_code(ram_addr_t ram_addr)
> * most usual is detecting writes to code regions which may invalidate
> * generated code.
> *
> - * Because we want other vCPUs to respond to changes straight away we
> - * update the te->addr_write field atomically. If the TLB entry has
> - * been changed by the vCPU in the mean time we skip the update.
> + * Other vCPUs might be reading their TLBs during guest execution, so we update
> + * te->addr_write with atomic_set. We don't need to worry about this for
> + * oversized guests as MTTCG is disabled for them.
> *
> - * As this function uses atomic accesses we also need to ensure
> - * updates to tlb_entries follow the same access rules. We don't need
> - * to worry about this for oversized guests as MTTCG is disabled for
> - * them.
> + * Called with tlb_lock held.
> */
> -
> -static void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start,
> - uintptr_t length)
> +static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry,
> + uintptr_t start, uintptr_t length)
> {
> -#if TCG_OVERSIZED_GUEST
> uintptr_t addr = tlb_entry->addr_write;
>
> if ((addr & (TLB_INVALID_MASK | TLB_MMIO | TLB_NOTDIRTY)) == 0) {
> addr &= TARGET_PAGE_MASK;
> addr += tlb_entry->addend;
> if ((addr - start) < length) {
> +#if TCG_OVERSIZED_GUEST
> tlb_entry->addr_write |= TLB_NOTDIRTY;
> - }
> - }
> #else
> - /* paired with atomic_mb_set in tlb_set_page_with_attrs */
> - uintptr_t orig_addr = atomic_mb_read(&tlb_entry->addr_write);
> - uintptr_t addr = orig_addr;
> -
> - if ((addr & (TLB_INVALID_MASK | TLB_MMIO | TLB_NOTDIRTY)) == 0) {
> - addr &= TARGET_PAGE_MASK;
> - addr += atomic_read(&tlb_entry->addend);
> - if ((addr - start) < length) {
> - uintptr_t notdirty_addr = orig_addr | TLB_NOTDIRTY;
> - atomic_cmpxchg(&tlb_entry->addr_write, orig_addr, notdirty_addr);
> + atomic_set(&tlb_entry->addr_write,
> + tlb_entry->addr_write | TLB_NOTDIRTY);
> +#endif
> }
> }
> -#endif
> }
>
> -/* For atomic correctness when running MTTCG we need to use the right
> - * primitives when copying entries */
> -static inline void copy_tlb_helper(CPUTLBEntry *d, CPUTLBEntry *s,
> - bool atomic_set)
> +/* Called with tlb_lock held */
> +static void copy_tlb_helper_locked(CPUTLBEntry *d, const CPUTLBEntry *s)
> {
> -#if TCG_OVERSIZED_GUEST
> *d = *s;
> -#else
> - if (atomic_set) {
> - d->addr_read = s->addr_read;
> - d->addr_code = s->addr_code;
> - atomic_set(&d->addend, atomic_read(&s->addend));
> - /* Pairs with flag setting in tlb_reset_dirty_range */
> - atomic_mb_set(&d->addr_write, atomic_read(&s->addr_write));
> - } else {
> - d->addr_read = s->addr_read;
> - d->addr_write = atomic_read(&s->addr_write);
> - d->addr_code = s->addr_code;
> - d->addend = atomic_read(&s->addend);
> - }
> -#endif
> +}
> +
> +static void copy_tlb_helper(CPUArchState *env, CPUTLBEntry *d, CPUTLBEntry *s)
> +{
> + assert_cpu_is_self(ENV_GET_CPU(env));
> + qemu_mutex_lock(&env->tlb_lock);
> + copy_tlb_helper_locked(d, s);
> + qemu_mutex_unlock(&env->tlb_lock);
> }
>
> /* This is a cross vCPU call (i.e. another vCPU resetting the flags of
> - * the target vCPU). As such care needs to be taken that we don't
> - * dangerously race with another vCPU update. The only thing actually
> - * updated is the target TLB entry ->addr_write flags.
> + * the target vCPU).
> + * We must take tlb_lock to avoid racing with another vCPU update. The only
> + * thing actually updated is the target TLB entry ->addr_write flags.
> */
> void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length)
> {
> @@ -528,22 +537,26 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length)
> int mmu_idx;
>
> env = cpu->env_ptr;
> + qemu_mutex_lock(&env->tlb_lock);
> for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
> unsigned int i;
>
> for (i = 0; i < CPU_TLB_SIZE; i++) {
> - tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i],
> - start1, length);
> + tlb_reset_dirty_range_locked(&env->tlb_table[mmu_idx][i], start1,
> + length);
> }
>
> for (i = 0; i < CPU_VTLB_SIZE; i++) {
> - tlb_reset_dirty_range(&env->tlb_v_table[mmu_idx][i],
> - start1, length);
> + tlb_reset_dirty_range_locked(&env->tlb_v_table[mmu_idx][i], start1,
> + length);
> }
> }
> + qemu_mutex_unlock(&env->tlb_lock);
> }
>
> -static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
> +/* Called with tlb_lock held */
> +static inline void tlb_set_dirty1_locked(CPUTLBEntry *tlb_entry,
> + target_ulong vaddr)
> {
> if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) {
> tlb_entry->addr_write = vaddr;
> @@ -562,16 +575,18 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr)
>
> vaddr &= TARGET_PAGE_MASK;
> i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
> + qemu_mutex_lock(&env->tlb_lock);
> for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
> - tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr);
> + tlb_set_dirty1_locked(&env->tlb_table[mmu_idx][i], vaddr);
> }
>
> for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
> int k;
> for (k = 0; k < CPU_VTLB_SIZE; k++) {
> - tlb_set_dirty1(&env->tlb_v_table[mmu_idx][k], vaddr);
> + tlb_set_dirty1_locked(&env->tlb_v_table[mmu_idx][k], vaddr);
> }
> }
> + qemu_mutex_unlock(&env->tlb_lock);
> }
>
> /* Our TLB does not support large pages, so remember the area covered by
> @@ -677,7 +692,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
> CPUTLBEntry *tv = &env->tlb_v_table[mmu_idx][vidx];
>
> /* Evict the old entry into the victim tlb. */
> - copy_tlb_helper(tv, te, true);
> + copy_tlb_helper(env, tv, te);
> env->iotlb_v[mmu_idx][vidx] = env->iotlb[mmu_idx][index];
> }
>
> @@ -729,9 +744,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
> }
> }
>
> - /* Pairs with flag setting in tlb_reset_dirty_range */
> - copy_tlb_helper(te, &tn, true);
> - /* atomic_mb_set(&te->addr_write, write_address); */
> + copy_tlb_helper(env, te, &tn);
> }
>
> /* Add a new TLB entry, but without specifying the memory
> @@ -895,6 +908,8 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index,
> size_t elt_ofs, target_ulong page)
> {
> size_t vidx;
> +
> + assert_cpu_is_self(ENV_GET_CPU(env));
> for (vidx = 0; vidx < CPU_VTLB_SIZE; ++vidx) {
> CPUTLBEntry *vtlb = &env->tlb_v_table[mmu_idx][vidx];
> target_ulong cmp = *(target_ulong *)((uintptr_t)vtlb + elt_ofs);
> @@ -903,9 +918,11 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index,
> /* Found entry in victim tlb, swap tlb and iotlb. */
> CPUTLBEntry tmptlb, *tlb = &env->tlb_table[mmu_idx][index];
>
> - copy_tlb_helper(&tmptlb, tlb, false);
> - copy_tlb_helper(tlb, vtlb, true);
> - copy_tlb_helper(vtlb, &tmptlb, true);
> + qemu_mutex_lock(&env->tlb_lock);
> + copy_tlb_helper_locked(&tmptlb, tlb);
> + copy_tlb_helper_locked(tlb, vtlb);
> + copy_tlb_helper_locked(vtlb, &tmptlb);
> + qemu_mutex_unlock(&env->tlb_lock);
>
> CPUIOTLBEntry tmpio, *io = &env->iotlb[mmu_idx][index];
> CPUIOTLBEntry *vio = &env->iotlb_v[mmu_idx][vidx];
--
Alex Bennée
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v2 4/4] cputlb: read CPUTLBEntry.addr_write atomically
2018-10-03 20:04 [Qemu-devel] [PATCH v2 0/4] per-TLB lock Emilio G. Cota
` (2 preceding siblings ...)
2018-10-03 20:04 ` [Qemu-devel] [PATCH v2 3/4] cputlb: serialize tlb updates with env->tlb_lock Emilio G. Cota
@ 2018-10-03 20:04 ` Emilio G. Cota
2018-10-04 4:01 ` Emilio G. Cota
2018-10-04 20:15 ` [Qemu-devel] [PATCH v2 0/4] per-TLB lock Alex Bennée
4 siblings, 1 reply; 12+ messages in thread
From: Emilio G. Cota @ 2018-10-03 20:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Paolo Bonzini, Richard Henderson, Alex Bennée
Updates can come from other threads, so readers that do not
take tlb_lock must use atomic_read to avoid undefined
behaviour (UB).
This and the previous commit result in a small performance decrease,
but this is a fair price for removing UB.
Host: Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz
- Before:
Performance counter stats for 'taskset -c 0 ../img/aarch64/die.sh' (10 runs):
7482.981146 task-clock (msec) # 0.998 CPUs utilized ( +- 0.09% )
31,565,219,958 cycles # 4.218 GHz ( +- 0.09% )
57,102,517,194 instructions # 1.81 insns per cycle ( +- 0.07% )
10,255,768,012 branches # 1370.546 M/sec ( +- 0.07% )
172,980,542 branch-misses # 1.69% of all branches ( +- 0.11% )
7.494710830 seconds time elapsed ( +- 0.09% )
- After:
Performance counter stats for 'taskset -c 0 ../img/aarch64/die.sh' (10 runs):
7649.735155 task-clock (msec) # 0.999 CPUs utilized ( +- 0.13% )
32,262,593,483 cycles # 4.217 GHz ( +- 0.13% )
58,487,065,236 instructions # 1.81 insns per cycle ( +- 0.06% )
10,561,549,557 branches # 1380.643 M/sec ( +- 0.06% )
173,995,793 branch-misses # 1.65% of all branches ( +- 0.12% )
7.660611466 seconds time elapsed ( +- 0.13% )
That is, a ~2% slowdown for the aarch64 bootup+shutdown test.
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
accel/tcg/softmmu_template.h | 16 ++++++++++------
include/exec/cpu_ldst.h | 2 +-
include/exec/cpu_ldst_template.h | 2 +-
accel/tcg/cputlb.c | 15 +++++++++------
4 files changed, 21 insertions(+), 14 deletions(-)
diff --git a/accel/tcg/softmmu_template.h b/accel/tcg/softmmu_template.h
index f060a693d4..1e50263871 100644
--- a/accel/tcg/softmmu_template.h
+++ b/accel/tcg/softmmu_template.h
@@ -277,7 +277,8 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
{
unsigned mmu_idx = get_mmuidx(oi);
int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
- target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
+ target_ulong tlb_addr =
+ atomic_read(&env->tlb_table[mmu_idx][index].addr_write);
unsigned a_bits = get_alignment_bits(get_memop(oi));
uintptr_t haddr;
@@ -292,7 +293,8 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE,
mmu_idx, retaddr);
}
- tlb_addr = env->tlb_table[mmu_idx][index].addr_write & ~TLB_INVALID_MASK;
+ tlb_addr = atomic_read(&env->tlb_table[mmu_idx][index].addr_write) &
+ ~TLB_INVALID_MASK;
}
/* Handle an IO access. */
@@ -321,7 +323,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
cannot evict the first. */
page2 = (addr + DATA_SIZE) & TARGET_PAGE_MASK;
index2 = (page2 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
- tlb_addr2 = env->tlb_table[mmu_idx][index2].addr_write;
+ tlb_addr2 = atomic_read(&env->tlb_table[mmu_idx][index2].addr_write);
if (!tlb_hit_page(tlb_addr2, page2)
&& !VICTIM_TLB_HIT(addr_write, page2)) {
tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE,
@@ -354,7 +356,8 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
{
unsigned mmu_idx = get_mmuidx(oi);
int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
- target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
+ target_ulong tlb_addr =
+ atomic_read(&env->tlb_table[mmu_idx][index].addr_write);
unsigned a_bits = get_alignment_bits(get_memop(oi));
uintptr_t haddr;
@@ -369,7 +372,8 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE,
mmu_idx, retaddr);
}
- tlb_addr = env->tlb_table[mmu_idx][index].addr_write & ~TLB_INVALID_MASK;
+ tlb_addr = atomic_read(&env->tlb_table[mmu_idx][index].addr_write) &
+ ~TLB_INVALID_MASK;
}
/* Handle an IO access. */
@@ -398,7 +402,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
cannot evict the first. */
page2 = (addr + DATA_SIZE) & TARGET_PAGE_MASK;
index2 = (page2 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
- tlb_addr2 = env->tlb_table[mmu_idx][index2].addr_write;
+ tlb_addr2 = atomic_read(&env->tlb_table[mmu_idx][index2].addr_write);
if (!tlb_hit_page(tlb_addr2, page2)
&& !VICTIM_TLB_HIT(addr_write, page2)) {
tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE,
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index 41ed0526e2..9581587ce1 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -426,7 +426,7 @@ static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
tlb_addr = tlbentry->addr_read;
break;
case 1:
- tlb_addr = tlbentry->addr_write;
+ tlb_addr = atomic_read(&tlbentry->addr_write);
break;
case 2:
tlb_addr = tlbentry->addr_code;
diff --git a/include/exec/cpu_ldst_template.h b/include/exec/cpu_ldst_template.h
index 4db2302962..ba7a11123c 100644
--- a/include/exec/cpu_ldst_template.h
+++ b/include/exec/cpu_ldst_template.h
@@ -176,7 +176,7 @@ glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
addr = ptr;
page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
mmu_idx = CPU_MMU_INDEX;
- if (unlikely(env->tlb_table[mmu_idx][page_index].addr_write !=
+ if (unlikely(atomic_read(&env->tlb_table[mmu_idx][page_index].addr_write) !=
(addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
oi = make_memop_idx(SHIFT, mmu_idx);
glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(env, addr, v, oi,
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 142a9cdf9e..adbeda0d3b 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -257,7 +257,7 @@ static inline bool tlb_hit_page_anyprot(CPUTLBEntry *tlb_entry,
target_ulong page)
{
return tlb_hit_page(tlb_entry->addr_read, page) ||
- tlb_hit_page(tlb_entry->addr_write, page) ||
+ tlb_hit_page(atomic_read(&tlb_entry->addr_write), page) ||
tlb_hit_page(tlb_entry->addr_code, page);
}
@@ -863,7 +863,7 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
tlb_fill(cpu, addr, size, MMU_DATA_STORE, mmu_idx, retaddr);
index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
- tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
+ tlb_addr = atomic_read(&env->tlb_table[mmu_idx][index].addr_write);
if (!(tlb_addr & ~(TARGET_PAGE_MASK | TLB_RECHECK))) {
/* RAM access */
uintptr_t haddr = addr + env->tlb_table[mmu_idx][index].addend;
@@ -912,7 +912,9 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index,
assert_cpu_is_self(ENV_GET_CPU(env));
for (vidx = 0; vidx < CPU_VTLB_SIZE; ++vidx) {
CPUTLBEntry *vtlb = &env->tlb_v_table[mmu_idx][vidx];
- target_ulong cmp = *(target_ulong *)((uintptr_t)vtlb + elt_ofs);
+ /* elt_ofs might correspond to .addr_write, so use atomic_read */
+ target_ulong cmp =
+ atomic_read((target_ulong *)((uintptr_t)vtlb + elt_ofs));
if (cmp == page) {
/* Found entry in victim tlb, swap tlb and iotlb. */
@@ -984,7 +986,8 @@ void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
uintptr_t retaddr)
{
int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
- target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
+ target_ulong tlb_addr =
+ atomic_read(&env->tlb_table[mmu_idx][index].addr_write);
if (!tlb_hit(tlb_addr, addr)) {
/* TLB entry is for a different page */
@@ -1004,7 +1007,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
size_t mmu_idx = get_mmuidx(oi);
size_t index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
CPUTLBEntry *tlbe = &env->tlb_table[mmu_idx][index];
- target_ulong tlb_addr = tlbe->addr_write;
+ target_ulong tlb_addr = atomic_read(&tlbe->addr_write);
TCGMemOp mop = get_memop(oi);
int a_bits = get_alignment_bits(mop);
int s_bits = mop & MO_SIZE;
@@ -1035,7 +1038,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
tlb_fill(ENV_GET_CPU(env), addr, 1 << s_bits, MMU_DATA_STORE,
mmu_idx, retaddr);
}
- tlb_addr = tlbe->addr_write & ~TLB_INVALID_MASK;
+ tlb_addr = atomic_read(&tlbe->addr_write) & ~TLB_INVALID_MASK;
}
/* Notice an IO access or a needs-MMU-lookup access */
--
2.17.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [Qemu-devel] [PATCH v2 4/4] cputlb: read CPUTLBEntry.addr_write atomically
2018-10-03 20:04 ` [Qemu-devel] [PATCH v2 4/4] cputlb: read CPUTLBEntry.addr_write atomically Emilio G. Cota
@ 2018-10-04 4:01 ` Emilio G. Cota
2018-10-04 4:03 ` Emilio G. Cota
0 siblings, 1 reply; 12+ messages in thread
From: Emilio G. Cota @ 2018-10-04 4:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Paolo Bonzini, Richard Henderson, Alex Bennée
On Wed, Oct 03, 2018 at 16:04:54 -0400, Emilio G. Cota wrote:
> Updates can come from other threads, so readers that do not
> take tlb_lock must use atomic_read to avoid undefined
> behaviour (UB).
>
> This and the previous commit result in a small performance decrease,
> but this is a fair price for removing UB.
(snip)
> That is, a ~2% slowdown for the aarch64 bootup+shutdown test.
I've run more tests. This slowdown is much more pronounced on
memory-heavy workloads. These are the numbers for SPEC06int:
Speedup over master
1.05 +-+--+----+----+----+----+----+----+---+----+----+----+----+----+--+-+
| +++ || +++ |
|tlb-lock-noatomic +++ | **| |+++ |
| +atomic | ++++ | **## | | |
1 +-+..+++...............++##.***#...|..**|#......**|................+-+
| ### ***++ ***# *+*# +++ **+# +++ **## |
| # # *+*# *|*# *+*# || ** # **## **|# |
| # # * *#+ *+*# * *# || ** # **+#+**|# +** ++### |
0.95 +-+..#.#.....*.*#......*.*#.*.*#.***#.**.#.**.#.**|#......**##***+#+-+
| # # * *# * *# * *# *|*# ** # ** # **+# **+#* * # |
| # # * *# * *# * *# *|*# ** # ** # ** #+++++ ** #* * # |
0.9 +-+***.#..+++*.*#......*.*#.*.*#.*+*#.**.#.**.#.**.#+**|..**.#*.*.#+-+
| * * #***##* *# * *# * *# * *# ** # ** # ** # **## ** #* * # |
| * * #* *+#* *# +++* *# * *# * *# ** # ** # ** # **|# ** #* * # |
| * * #* * #* *# ***# * *# * *# *+*# ** # ** # ** # **+# ** #* * # |
0.85 +-+*.*.#*.*.#*.*#.*.*#+*.*#.*.*#.*.*#.**.#.**.#.**.#.**.#.**.#*.*.#+-+
| * * #* * #* *# * *# * *# * *# * *# ** # ** # ** # ** # ** #* * # |
| * * #* * #* *# * *# * *# * *# * *# ** # ** # ** # ** # ** #* * # |
| * * #* * #* *# * *# * *# * *# * *# ** # ** # ** # ** # ** #* * # |
0.8 +-+***##***##***#-***#-***#-***#-***#-**##-**##-**##-**##-**##***##+-+
401.bzi403.g429445.g456.462.libq464.h471.omn4483.xalancbgeomean
That is, a 5% average slowdown, with a max slowdown of ~14% for
mcf :-(
I'll profile tomorrow and see where the slowdown comes from.
If the lock is the issue, we might be better off shifting
all the work to the cross-vCPU call (e.g. doing a round of
synchronous cross-vCPU calls via run_on_cpu), if the assumption
that those calls are very rare is correct.
Emilio
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Qemu-devel] [PATCH v2 0/4] per-TLB lock
2018-10-03 20:04 [Qemu-devel] [PATCH v2 0/4] per-TLB lock Emilio G. Cota
` (3 preceding siblings ...)
2018-10-03 20:04 ` [Qemu-devel] [PATCH v2 4/4] cputlb: read CPUTLBEntry.addr_write atomically Emilio G. Cota
@ 2018-10-04 20:15 ` Alex Bennée
4 siblings, 0 replies; 12+ messages in thread
From: Alex Bennée @ 2018-10-04 20:15 UTC (permalink / raw)
To: Emilio G. Cota; +Cc: qemu-devel, Paolo Bonzini, Richard Henderson
Emilio G. Cota <cota@braap.org> writes:
> v1: https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg00395.html
>
> Changes since v1:
>
> - Rebase on master
>
> - Expand lock usage to other tlb_table/tlb_v_table updates, which I
> missed in v1
>
> - Fix assert_cpu_is_self macro
>
> - Add comment on why the owner thread doesn't need to use atomic_set
> for updates
>
> - Add more calls to assert_cpu_is_self macro, which together with
> the added comment should make the code simpler to understand
>
> - Include perf numbers in the last patch
>
> The series is checkpatch-clean. You can fetch the code from:
> https://github.com/cota/qemu/tree/tlb-lock-v2
Weird build failure aside I gave it a good build test soak which usually
trips up TLB issues.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
^ permalink raw reply [flat|nested] 12+ messages in thread