From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52978) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g85ZM-00085X-45 for qemu-devel@nongnu.org; Thu, 04 Oct 2018 11:29:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g85ZK-0004z9-AN for qemu-devel@nongnu.org; Thu, 04 Oct 2018 11:29:39 -0400 From: Cornelia Huck Date: Thu, 4 Oct 2018 17:28:47 +0200 Message-Id: <20181004152857.14525-6-cohuck@redhat.com> In-Reply-To: <20181004152857.14525-1-cohuck@redhat.com> References: <20181004152857.14525-1-cohuck@redhat.com> Subject: [Qemu-devel] [PULL 05/15] target/s390x: exception on non-aligned LPSW(E) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Christian Borntraeger , Alexander Graf , Richard Henderson , David Hildenbrand , Thomas Huth , qemu-s390x@nongnu.org, qemu-devel@nongnu.org, Pavel Zbitskiy , Cornelia Huck From: Pavel Zbitskiy Both LPSW and LPSWE should raise a specification exception when their operand is not doubleword aligned. Signed-off-by: Pavel Zbitskiy Message-Id: <20180902003322.3428-3-pavel.zbitskiy@gmail.com> Reviewed-by: David Hildenbrand Signed-off-by: Cornelia Huck --- target/s390x/translate.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 7363aabf3a..59b1e5893c 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -2835,7 +2835,8 @@ static DisasJumpType op_lpsw(DisasContext *s, DisasOps *o) t1 = tcg_temp_new_i64(); t2 = tcg_temp_new_i64(); - tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), + MO_TEUL | MO_ALIGN_8); tcg_gen_addi_i64(o->in2, o->in2, 4); tcg_gen_qemu_ld32u(t2, o->in2, get_mem_index(s)); /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */ @@ -2855,7 +2856,8 @@ static DisasJumpType op_lpswe(DisasContext *s, DisasOps *o) t1 = tcg_temp_new_i64(); t2 = tcg_temp_new_i64(); - tcg_gen_qemu_ld64(t1, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), + MO_TEQ | MO_ALIGN_8); tcg_gen_addi_i64(o->in2, o->in2, 8); tcg_gen_qemu_ld64(t2, o->in2, get_mem_index(s)); gen_helper_load_psw(cpu_env, t1, t2); -- 2.14.4