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From: "Emilio G. Cota" <cota@braap.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "QEMU Developers" <qemu-devel@nongnu.org>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Richard Henderson" <richard.henderson@linaro.org>
Subject: Re: [Qemu-devel] [PATCH v5 1/6] target/alpha: remove tlb_flush from alpha_cpu_initfn
Date: Tue, 9 Oct 2018 14:20:53 -0400	[thread overview]
Message-ID: <20181009182053.GA28943@flamenco> (raw)
In-Reply-To: <CAFEAcA8DyV6_BfRZT2_9K1PKNkPnLqw8e=55uJ3R1r5+ejkRFw@mail.gmail.com>

On Tue, Oct 09, 2018 at 18:55:30 +0100, Peter Maydell wrote:
> On 9 October 2018 at 18:45, Emilio G. Cota <cota@braap.org> wrote:
(snip)
> > @@ -201,7 +201,6 @@ static void alpha_cpu_initfn(Object *obj)
> >      CPUAlphaState *env = &cpu->env;
> >
> >      cs->env_ptr = env;
> > -    tlb_flush(cs);
> >
> >      env->lock_addr = -1;
> >  #if defined(CONFIG_USER_ONLY)
> > --
> > 2.17.1
> 
> Definitely agreed that we don't want to tlb_flush in the
> target cpu initfn.
> 
> 
> What's the codepath by which tlb_flush gets called on
> cpu reset? I had a quick look but couldn't find it...

>From cpu.c:

static void cpu_common_reset(CPUState *cpu)
{
    CPUClass *cc = CPU_GET_CLASS(cpu);
...
    if (tcg_enabled()) {
        cpu_tb_jmp_cache_clear(cpu);

        tcg_flush_softmmu_tlb(cpu);
    }
}

tcg_flush_softmmu_tlb is defined in translate-all.c:

/* This is a wrapper for common code that can not use CONFIG_SOFTMMU */
void tcg_flush_softmmu_tlb(CPUState *cs)
{
#ifdef CONFIG_SOFTMMU
    tlb_flush(cs);
#endif
}

> (The other dubious-looking bit of flushing in the
> target/alpha code is the code that generates calls
> to tb_flush()... we have very few calls to tb_flush
> outside the 'core' code and I suspect they could all
> be avoided.)

If the comment below is accurate, seems fair enough.
tb_flush is only called from target/alpha through a helper,
generated by:

        /* PALBR */
        tcg_gen_st_i64(vb, cpu_env, offsetof(CPUAlphaState, palbr));
        /* Changing the PAL base register implies un-chaining all of the TBs
           that ended with a CALL_PAL.  Since the base register usually only
           changes during boot, flushing everything works well.  */
        gen_helper_tb_flush(cpu_env);
        return DISAS_PC_STALE;

Thanks,

		Emilio

  reply	other threads:[~2018-10-09 18:21 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-09 17:45 [Qemu-devel] [PATCH v5 0/6] per-TLB lock Emilio G. Cota
2018-10-09 17:45 ` [Qemu-devel] [PATCH v5 1/6] target/alpha: remove tlb_flush from alpha_cpu_initfn Emilio G. Cota
2018-10-09 17:55   ` Peter Maydell
2018-10-09 18:20     ` Emilio G. Cota [this message]
2018-10-09 18:25       ` Peter Maydell
2018-10-09 20:48         ` Richard Henderson
2018-10-09 18:14   ` Alex Bennée
2018-10-09 20:49   ` Richard Henderson
2018-10-09 17:45 ` [Qemu-devel] [PATCH v5 2/6] target/unicore32: remove tlb_flush from uc32_init_fn Emilio G. Cota
2018-10-09 18:14   ` Alex Bennée
2018-10-09 20:49   ` Richard Henderson
2018-10-09 17:45 ` [Qemu-devel] [PATCH v5 3/6] exec: introduce tlb_init Emilio G. Cota
2018-10-09 20:49   ` Richard Henderson
2018-10-09 17:45 ` [Qemu-devel] [PATCH v5 4/6] cputlb: fix assert_cpu_is_self macro Emilio G. Cota
2018-10-09 17:45 ` [Qemu-devel] [PATCH v5 5/6] cputlb: serialize tlb updates with env->tlb_lock Emilio G. Cota
2018-10-09 17:45 ` [Qemu-devel] [PATCH v5 6/6] cputlb: read CPUTLBEntry.addr_write atomically Emilio G. Cota
2018-10-11 22:22 ` [Qemu-devel] [PATCH v5 0/6] per-TLB lock Richard Henderson

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