From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39807) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gALFi-0002wJ-G4 for qemu-devel@nongnu.org; Wed, 10 Oct 2018 16:38:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gALFh-0002kD-K4 for qemu-devel@nongnu.org; Wed, 10 Oct 2018 16:38:42 -0400 From: Aaron Lindsay Date: Wed, 10 Oct 2018 16:37:33 -0400 Message-Id: <20181010203735.27918-13-aclindsa@gmail.com> In-Reply-To: <20181010203735.27918-1-aclindsa@gmail.com> References: <20181010203735.27918-1-aclindsa@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v6 12/14] target/arm: PMU: Set PMCR.N to 4 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Cc: qemu-devel@nongnu.org, Michael Spradling , Digant Desai , Aaron Lindsay , Aaron Lindsay This both advertises that we support four counters and enables them because the pmu_num_counters() reads this value from PMCR. Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d6501de1ba..89ceb34cb9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1706,7 +1706,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .access = PL1_W, .type = ARM_CP_NOP }, /* Performance monitors are implementation defined in v7, * but with an ARM recommended set of registers, which we - * follow (although we don't actually implement any counters) + * follow. * * Performance registers fall into three categories: * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) @@ -5412,8 +5412,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) } if (arm_feature(env, ARM_FEATURE_V7)) { /* v7 performance monitor control register: same implementor - * field as main ID register, and we implement only the cycle - * count register. + * field as main ID register, and we implement four counters in + * addition to the cycle count register. */ unsigned int i, pmcrn = 4; ARMCPRegInfo pmcr = { @@ -5430,7 +5430,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access = PL0_RW, .accessfn = pmreg_access, .type = ARM_CP_IO, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), - .resetvalue = cpu->midr & 0xff000000, + .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT), .writefn = pmcr_write, .raw_writefn = raw_write, }; define_one_arm_cp_reg(cpu, &pmcr); -- 2.19.1