From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PATCH 06/20] target/arm: Use gvec for NEON VDUP
Date: Thu, 11 Oct 2018 13:51:52 -0700 [thread overview]
Message-ID: <20181011205206.3552-7-richard.henderson@linaro.org> (raw)
In-Reply-To: <20181011205206.3552-1-richard.henderson@linaro.org>
Also introduces neon_element_offset to find the env offset
of a specific element within a neon register.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 63 ++++++++++++++++++++++++------------------
1 file changed, 36 insertions(+), 27 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index d59ffa1c67..4ac526e298 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1585,6 +1585,25 @@ neon_reg_offset (int reg, int n)
return vfp_reg_offset(0, sreg);
}
+/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
+ * where 0 is the least significant end of the register.
+ */
+static inline long
+neon_element_offset(int reg, int element, TCGMemOp size)
+{
+ int element_size = 1 << size;
+ int ofs = element * element_size;
+#ifdef HOST_WORDS_BIGENDIAN
+ /* Calculate the offset assuming fully little-endian,
+ * then XOR to account for the order of the 8-byte units.
+ */
+ if (element_size < 8) {
+ ofs ^= 8 - element_size;
+ }
+#endif
+ return neon_reg_offset(reg, 0) + ofs;
+}
+
static TCGv_i32 neon_load_reg(int reg, int pass)
{
TCGv_i32 tmp = tcg_temp_new_i32();
@@ -3432,17 +3451,10 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
tmp = load_reg(s, rd);
if (insn & (1 << 23)) {
/* VDUP */
- if (size == 0) {
- gen_neon_dup_u8(tmp, 0);
- } else if (size == 1) {
- gen_neon_dup_low16(tmp);
- }
- for (n = 0; n <= pass * 2; n++) {
- tmp2 = tcg_temp_new_i32();
- tcg_gen_mov_i32(tmp2, tmp);
- neon_store_reg(rn, n, tmp2);
- }
- neon_store_reg(rn, n, tmp);
+ int vec_size = pass ? 16 : 8;
+ tcg_gen_gvec_dup_i32(size, neon_reg_offset(rn, 0),
+ vec_size, vec_size, tmp);
+ tcg_temp_free_i32(tmp);
} else {
/* VMOV */
switch (size) {
@@ -7755,28 +7767,25 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
tcg_temp_free_i32(tmp);
} else if ((insn & 0x380) == 0) {
/* VDUP */
+ int element;
+ TCGMemOp size;
+
if ((insn & (7 << 16)) == 0 || (q && (rd & 1))) {
return 1;
}
- if (insn & (1 << 19)) {
- tmp = neon_load_reg(rm, 1);
- } else {
- tmp = neon_load_reg(rm, 0);
- }
if (insn & (1 << 16)) {
- gen_neon_dup_u8(tmp, ((insn >> 17) & 3) * 8);
+ size = MO_8;
+ element = (insn >> 17) & 7;
} else if (insn & (1 << 17)) {
- if ((insn >> 18) & 1)
- gen_neon_dup_high16(tmp);
- else
- gen_neon_dup_low16(tmp);
+ size = MO_16;
+ element = (insn >> 18) & 3;
+ } else {
+ size = MO_32;
+ element = (insn >> 19) & 1;
}
- for (pass = 0; pass < (q ? 4 : 2); pass++) {
- tmp2 = tcg_temp_new_i32();
- tcg_gen_mov_i32(tmp2, tmp);
- neon_store_reg(rd, pass, tmp2);
- }
- tcg_temp_free_i32(tmp);
+ tcg_gen_gvec_dup_mem(size, neon_reg_offset(rd, 0),
+ neon_element_offset(rm, element, size),
+ q ? 16 : 8, q ? 16 : 8);
} else {
return 1;
}
--
2.17.1
next prev parent reply other threads:[~2018-10-11 20:52 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-11 20:51 [Qemu-devel] [PATCH 00/20] target/arm: Convert some neon insns to gvec Richard Henderson
2018-10-11 20:51 ` [Qemu-devel] [PATCH 01/20] target/arm: Hoist address increment for vector memory ops Richard Henderson
2018-10-11 20:51 ` [Qemu-devel] [PATCH 02/20] target/arm: Don't call tcg_clear_temp_count Richard Henderson
2018-10-11 23:35 ` Philippe Mathieu-Daudé
2018-10-11 20:51 ` [Qemu-devel] [PATCH 03/20] target/arm: Use tcg_gen_gvec_dup_i64 for LD[1-4]R Richard Henderson
2018-10-11 20:51 ` [Qemu-devel] [PATCH 04/20] target/arm: Promote consecutive memory ops for aa64 Richard Henderson
2018-10-11 20:51 ` [Qemu-devel] [PATCH 05/20] target/arm: Mark some arrays const Richard Henderson
2018-10-11 23:34 ` Philippe Mathieu-Daudé
2018-10-19 13:05 ` Peter Maydell
2018-10-11 20:51 ` Richard Henderson [this message]
2018-10-11 20:51 ` [Qemu-devel] [PATCH 07/20] target/arm: Use gvec for NEON VMOV, VMVN, VBIC & VORR (immediate) Richard Henderson
2018-10-11 20:51 ` [Qemu-devel] [PATCH 08/20] target/arm: Use gvec for NEON_3R_LOGIC insns Richard Henderson
2018-10-11 20:51 ` [Qemu-devel] [PATCH 09/20] target/arm: Use gvec for NEON_3R_VADD_VSUB insns Richard Henderson
2018-10-11 20:51 ` [Qemu-devel] [PATCH 10/20] target/arm: Use gvec for NEON_2RM_VMN, NEON_2RM_VNEG Richard Henderson
2018-10-11 20:51 ` [Qemu-devel] [PATCH 11/20] target/arm: Use gvec for NEON_3R_VMUL Richard Henderson
2018-10-11 20:51 ` [Qemu-devel] [PATCH 12/20] target/arm: Use gvec for VSHR, VSHL Richard Henderson
2018-10-11 20:51 ` [Qemu-devel] [PATCH 13/20] target/arm: Use gvec for VSRA Richard Henderson
2018-10-11 20:52 ` [Qemu-devel] [PATCH 14/20] target/arm: Use gvec for VSRI, VSLI Richard Henderson
2018-10-11 20:52 ` [Qemu-devel] [PATCH 15/20] target/arm: Use gvec for NEON_3R_VML Richard Henderson
2018-10-11 20:52 ` [Qemu-devel] [PATCH 16/20] target/arm: Use gvec for NEON_3R_VTST_VCEQ, NEON_3R_VCGT, NEON_3R_VCGE Richard Henderson
2018-10-11 20:52 ` [Qemu-devel] [PATCH 17/20] target/arm: Use gvec for NEON VLD all lanes Richard Henderson
2018-10-19 13:05 ` Peter Maydell
2018-10-11 20:52 ` [Qemu-devel] [PATCH 18/20] target/arm: Reorg NEON VLD/VST all elements Richard Henderson
2018-10-19 13:50 ` Peter Maydell
2018-10-19 15:15 ` Richard Henderson
2018-10-11 20:52 ` [Qemu-devel] [PATCH 19/20] target/arm: Promote consecutive memory ops for aa32 Richard Henderson
2018-10-19 5:17 ` Philippe Mathieu-Daudé
2018-10-11 20:52 ` [Qemu-devel] [PATCH 20/20] target/arm: Reorg NEON VLD/VST single element to one lane Richard Henderson
2018-10-19 13:51 ` [Qemu-devel] [PATCH 00/20] target/arm: Convert some neon insns to gvec Peter Maydell
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