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From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: mjc@sifive.com, palmer@sifive.com, sagark@eecs.berkeley.edu,
	kbastian@mail.uni-paderborn.de
Cc: qemu-devel@nongnu.org, peer.adelt@hni.uni-paderborn.de,
	Alistair.Francis@wdc.com
Subject: [Qemu-devel] [PATCH 26/28] target/riscv: Remove gen_system()
Date: Fri, 12 Oct 2018 19:30:45 +0200	[thread overview]
Message-ID: <20181012173047.25420-27-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <20181012173047.25420-1-kbastian@mail.uni-paderborn.de>

with all 16 bit insns moved to decodetree no path is falling back to
gen_system(), so we can remove it.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
 target/riscv/translate.c | 32 --------------------------------
 1 file changed, 32 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 5e24ec49a0..86ca885c7e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -305,34 +305,6 @@ static void gen_set_rm(DisasContext *ctx, int rm)
     tcg_temp_free_i32(t0);
 }
 
-
-static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
-                      int rd, int rs1, int csr)
-{
-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-
-    switch (opc) {
-    case OPC_RISC_ECALL:
-        switch (csr) {
-        case 0x0: /* ECALL */
-            /* always generates U-level ECALL, fixed in do_interrupt handler */
-            generate_exception(ctx, RISCV_EXCP_U_ECALL);
-            tcg_gen_exit_tb(NULL, 0); /* no chaining */
-            ctx->base.is_jmp = DISAS_NORETURN;
-            break;
-        case 0x1: /* EBREAK */
-            generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
-            tcg_gen_exit_tb(NULL, 0); /* no chaining */
-            ctx->base.is_jmp = DISAS_NORETURN;
-            break;
-        default:
-            gen_exception_illegal(ctx);
-            break;
-        }
-        break;
-    }
-}
-
 #define EX_SH(amount) \
     static int64_t ex_shift_##amount(int imm) \
     {                                         \
@@ -455,10 +427,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
     rd = GET_RD(ctx->opcode);
 
     switch (op) {
-    case OPC_RISC_SYSTEM:
-        gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
-                   (ctx->opcode & 0xFFF00000) >> 20);
-        break;
     default:
         gen_exception_illegal(ctx);
         break;
-- 
2.19.1

  parent reply	other threads:[~2018-10-12 17:31 UTC|newest]

Thread overview: 66+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-12 17:30 [Qemu-devel] [PATCH 00/28] target/riscv: Convert to decodetree Bastian Koppelmann
2018-10-12 17:30 ` [Qemu-devel] [PATCH 01/28] targer/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
2018-10-12 18:03   ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 02/28] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
2018-10-12 18:18   ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 03/28] target/riscv: Convert RVXI load/store " Bastian Koppelmann
2018-10-12 18:24   ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 04/28] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
2018-10-12 18:46   ` Richard Henderson
2018-10-19 11:00     ` Bastian Koppelmann
2018-10-19 18:18       ` Palmer Dabbelt
2018-10-12 17:30 ` [Qemu-devel] [PATCH 05/28] target/riscv: Convert RVXI fence " Bastian Koppelmann
2018-10-12 19:17   ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 06/28] target/riscv: Convert RVXI csr " Bastian Koppelmann
2018-10-13 16:36   ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 07/28] target/riscv: Convert RVXM " Bastian Koppelmann
2018-10-13 16:39   ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 08/28] target/riscv: Convert RV32A " Bastian Koppelmann
2018-10-13 16:50   ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 09/28] target/riscv: Convert RV64A " Bastian Koppelmann
2018-10-13 16:51   ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 10/28] target/riscv: Convert RV32F " Bastian Koppelmann
2018-10-13 17:33   ` Richard Henderson
2018-10-13 17:41   ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 11/28] target/riscv: Convert RV64F " Bastian Koppelmann
2018-10-13 17:37   ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 12/28] target/riscv: Convert RV32D " Bastian Koppelmann
2018-10-13 17:42   ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 13/28] target/riscv: Convert RV64D " Bastian Koppelmann
2018-10-13 17:44   ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 14/28] target/riscv: Convert RV priv " Bastian Koppelmann
2018-10-13 17:52   ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 15/28] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
2018-10-13 18:18   ` Richard Henderson
2018-10-19 12:49     ` Bastian Koppelmann
2018-10-12 17:30 ` [Qemu-devel] [PATCH 16/28] target/riscv: Convert quadrant 1 " Bastian Koppelmann
2018-10-13 18:53   ` Richard Henderson
2018-10-19 13:20     ` Bastian Koppelmann
2018-10-19 15:28     ` Bastian Koppelmann
2018-10-19 15:38       ` Richard Henderson
2018-10-19 18:49       ` Palmer Dabbelt
2018-10-12 17:30 ` [Qemu-devel] [PATCH 17/28] target/riscv: Convert quadrant 2 " Bastian Koppelmann
2018-10-13 19:34   ` Richard Henderson
2018-10-19 15:10     ` Bastian Koppelmann
2018-10-12 17:30 ` [Qemu-devel] [PATCH 18/28] target/riscv: Remove gen_jalr() Bastian Koppelmann
2018-10-13 19:37   ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 19/28] target/riscv: Replace gen_branch() with trans_branch() Bastian Koppelmann
2018-10-13 19:39   ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 20/28] target/riscv: Replace gen_load() with trans_load() Bastian Koppelmann
2018-10-13 19:44   ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 21/28] target/riscv: Replace gen_store() with trans_store() Bastian Koppelmann
2018-10-13 19:45   ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 22/28] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
2018-10-13 19:54   ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 23/28] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
2018-10-13 19:55   ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 24/28] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann
2018-10-13 19:57   ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 25/28] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
2018-10-13 20:00   ` Richard Henderson
2018-10-12 17:30 ` Bastian Koppelmann [this message]
2018-10-13 20:00   ` [Qemu-devel] [PATCH 26/28] target/riscv: Remove gen_system() Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 27/28] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
2018-10-13 20:01   ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 28/28] target/riscv: Replace gen_exception_illegal with return false Bastian Koppelmann
2018-10-13 20:04   ` Richard Henderson

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