From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40107) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB1Ht-00020U-Ge for qemu-devel@nongnu.org; Fri, 12 Oct 2018 13:31:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB1Hs-0000UK-0H for qemu-devel@nongnu.org; Fri, 12 Oct 2018 13:31:45 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:37152) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB1Hr-0000GQ-Od for qemu-devel@nongnu.org; Fri, 12 Oct 2018 13:31:43 -0400 From: Bastian Koppelmann Date: Fri, 12 Oct 2018 19:30:46 +0200 Message-Id: <20181012173047.25420-28-kbastian@mail.uni-paderborn.de> In-Reply-To: <20181012173047.25420-1-kbastian@mail.uni-paderborn.de> References: <20181012173047.25420-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH 27/28] target/riscv: Remove decode_RV32_64G() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: mjc@sifive.com, palmer@sifive.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de Cc: qemu-devel@nongnu.org, peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com decodetree handles all instructions now so the fallback is not necessary anymore. Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/translate.c | 23 ----------------------- 1 file changed, 23 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 86ca885c7e..8ef943f6c8 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -412,27 +412,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn); #include "decode_insn16.inc.c" #include "insn_trans/trans_rvc.inc.c" -static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) -{ - int rs1, rd; - uint32_t op; - - /* We do not do misaligned address check here: the address should never be - * misaligned at this point. Instructions that set PC must do the check, - * since epc must be the address of the instruction that caused us to - * perform the misaligned instruction fetch */ - - op = MASK_OP_MAJOR(ctx->opcode); - rs1 = GET_RS1(ctx->opcode); - rd = GET_RD(ctx->opcode); - - switch (op) { - default: - gen_exception_illegal(ctx); - break; - } -} - static void decode_opc(CPURISCVState *env, DisasContext *ctx) { /* check for compressed insn */ @@ -448,8 +427,6 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx) } else { ctx->pc_succ_insn = ctx->base.pc_next + 4; if (!decode_insn32(ctx, ctx->opcode)) { - /* fallback to old decoder */ - decode_RV32_64G(env, ctx); } } } -- 2.19.1