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Date: Sun, 14 Oct 2018 18:41:40 +0200
From: Fredrik Noring <noring@nocrew.org>
Message-ID: <20181014164140.GB2319@sx9>
References: <20181014142928.2784-1-f4bug@amsat.org>
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In-Reply-To: <20181014142928.2784-1-f4bug@amsat.org>
Subject: Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific
 three-operand MADD and MADDU
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To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= <f4bug@amsat.org>
Cc: "Maciej W . Rozycki" <macro@linux-mips.org>, Richard Henderson <richard.henderson@linaro.org>, Aleksandar Markovic <amarkovic@wavecomp.com>, Aurelien Jarno <aurelien@aurel32.net>, qemu-devel@nongnu.org, =?utf-8?Q?J=C3=BCrgen?= Urban <JuergenUrban@gmx.de>

Hi Philippe,

> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -3843,6 +3843,46 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,

What about documenting MADD and MADDU along with MULT and MULTU in the
note above?

> +    case OPC_MADD:

This case is unreachable, because gen_mul_txx9 will never be called for
OPC_MADD.

> +            TCGv_i64 t2 = tcg_temp_new_i64();
> +            TCGv_i64 t3 = tcg_temp_new_i64();

The MADD (and MADDU) instructions are defined to multiply 32-bit integers
in the C790 manual. Are 64-bit integers required to perform this with QEMU?

> +            gen_move_low32(cpu_LO[acc], t2);
> +            gen_move_high32(cpu_HI[acc], t2);
> +            if (rd) {
> +                gen_move_low32(cpu_gpr[rd], t2);

Are LO, HI and GPR[rd] sign-extended to 64 bits when required?

> +    case OPC_MADDU:

As above, this case is unreachable, because gen_mul_txx9 will never be
called for OPC_MADDU.

> +            gen_move_low32(cpu_LO[acc], t2);
> +            gen_move_high32(cpu_HI[acc], t2);
> +            if (rd) {
> +                gen_move_low32(cpu_gpr[rd], t2);

As above, are LO, HI and GPR[rd] sign-extended to 64 bits when required?

Fredrik