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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 09/19] net: cadence_gem: Add macro with max number of descriptor words
Date: Tue, 16 Oct 2018 16:23:15 +0100	[thread overview]
Message-ID: <20181016152325.31367-10-peter.maydell@linaro.org> (raw)
In-Reply-To: <20181016152325.31367-1-peter.maydell@linaro.org>

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Add macro with max number of DMA descriptor words.
No functional change.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20181011021931.4249-5-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/net/cadence_gem.h | 5 ++++-
 hw/net/cadence_gem.c         | 4 ++--
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
index 633d564dc3b..b33ef6513b9 100644
--- a/include/hw/net/cadence_gem.h
+++ b/include/hw/net/cadence_gem.h
@@ -32,6 +32,9 @@
 
 #define CADENCE_GEM_MAXREG        (0x00000800 / 4) /* Last valid GEM address */
 
+/* Max number of words in a DMA descriptor.  */
+#define DESC_MAX_NUM_WORDS              2
+
 #define MAX_PRIORITY_QUEUES             8
 #define MAX_TYPE1_SCREENERS             16
 #define MAX_TYPE2_SCREENERS             16
@@ -74,7 +77,7 @@ typedef struct CadenceGEMState {
 
     uint8_t can_rx_state; /* Debug only */
 
-    uint32_t rx_desc[MAX_PRIORITY_QUEUES][2];
+    uint32_t rx_desc[MAX_PRIORITY_QUEUES][DESC_MAX_NUM_WORDS];
 
     bool sar_active[4];
 } CadenceGEMState;
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 31f3fe0e816..4d769b02440 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1042,7 +1042,7 @@ static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet,
  */
 static void gem_transmit(CadenceGEMState *s)
 {
-    uint32_t desc[2];
+    uint32_t desc[DESC_MAX_NUM_WORDS];
     hwaddr packet_desc_addr;
     uint8_t     tx_packet[2048];
     uint8_t     *p;
@@ -1108,7 +1108,7 @@ static void gem_transmit(CadenceGEMState *s)
 
             /* Last descriptor for this packet; hand the whole thing off */
             if (tx_desc_get_last(desc)) {
-                uint32_t desc_first[2];
+                uint32_t desc_first[DESC_MAX_NUM_WORDS];
 
                 /* Modify the 1st descriptor of this packet to be owned by
                  * the processor.
-- 
2.19.0

  parent reply	other threads:[~2018-10-16 15:23 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-16 15:23 [Qemu-devel] [PULL 00/19] target-arm queue Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 01/19] hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 02/19] target/arm: Fix aarch64_sve_change_el wrt EL0 Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 03/19] target/arm: Define fields of ISAR registers Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 04/19] target/arm: Align cortex-r5 id_isar0 Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 05/19] target/arm: Fix cortex-a7 id_isar0 Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 06/19] net: cadence_gem: Disable TSU feature bit Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 07/19] net: cadence_gem: Announce availability of priority queues Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 08/19] net: cadence_gem: Use uint32_t for 32bit descriptor words Peter Maydell
2018-10-16 15:23 ` Peter Maydell [this message]
2018-10-16 15:23 ` [Qemu-devel] [PULL 10/19] net: cadence_gem: Add support for extended descriptors Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 11/19] net: cadence_gem: Add support for selecting the DMA MemoryRegion Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 12/19] net: cadence_gem: Implement support for 64bit descriptor addresses Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 13/19] net: cadence_gem: Announce 64bit addressing support Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 14/19] target-arm: powerctl: Enable HVC when starting CPUs to EL2 Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 15/19] target/arm: Add the Cortex-A72 Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 16/19] target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 17/19] target/arm: Mask PMOVSR writes based on supported counters Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 18/19] target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 19/19] coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls Peter Maydell

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