From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 13/19] net: cadence_gem: Announce 64bit addressing support
Date: Tue, 16 Oct 2018 16:23:19 +0100 [thread overview]
Message-ID: <20181016152325.31367-14-peter.maydell@linaro.org> (raw)
In-Reply-To: <20181016152325.31367-1-peter.maydell@linaro.org>
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Announce 64bit addressing support.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20181011021931.4249-9-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/net/cadence_gem.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 550225c15be..7f96de4affa 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -142,6 +142,7 @@
#define GEM_DESCONF4 (0x0000028C/4)
#define GEM_DESCONF5 (0x00000290/4)
#define GEM_DESCONF6 (0x00000294/4)
+#define GEM_DESCONF6_64B_MASK (1U << 23)
#define GEM_DESCONF7 (0x00000298/4)
#define GEM_INT_Q1_STATUS (0x00000400 / 4)
@@ -1300,7 +1301,7 @@ static void gem_reset(DeviceState *d)
s->regs[GEM_DESCONF] = 0x02500111;
s->regs[GEM_DESCONF2] = 0x2ab13fff;
s->regs[GEM_DESCONF5] = 0x002f2045;
- s->regs[GEM_DESCONF6] = 0x0;
+ s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK;
queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1);
s->regs[GEM_DESCONF6] |= queues_mask;
--
2.19.0
next prev parent reply other threads:[~2018-10-16 15:24 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-16 15:23 [Qemu-devel] [PULL 00/19] target-arm queue Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 01/19] hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 02/19] target/arm: Fix aarch64_sve_change_el wrt EL0 Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 03/19] target/arm: Define fields of ISAR registers Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 04/19] target/arm: Align cortex-r5 id_isar0 Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 05/19] target/arm: Fix cortex-a7 id_isar0 Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 06/19] net: cadence_gem: Disable TSU feature bit Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 07/19] net: cadence_gem: Announce availability of priority queues Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 08/19] net: cadence_gem: Use uint32_t for 32bit descriptor words Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 09/19] net: cadence_gem: Add macro with max number of " Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 10/19] net: cadence_gem: Add support for extended descriptors Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 11/19] net: cadence_gem: Add support for selecting the DMA MemoryRegion Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 12/19] net: cadence_gem: Implement support for 64bit descriptor addresses Peter Maydell
2018-10-16 15:23 ` Peter Maydell [this message]
2018-10-16 15:23 ` [Qemu-devel] [PULL 14/19] target-arm: powerctl: Enable HVC when starting CPUs to EL2 Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 15/19] target/arm: Add the Cortex-A72 Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 16/19] target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 17/19] target/arm: Mask PMOVSR writes based on supported counters Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 18/19] target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 19/19] coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls Peter Maydell
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