From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 19/19] coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
Date: Tue, 16 Oct 2018 16:23:25 +0100 [thread overview]
Message-ID: <20181016152325.31367-20-peter.maydell@linaro.org> (raw)
In-Reply-To: <20181016152325.31367-1-peter.maydell@linaro.org>
Add a new Coccinelle script which replaces uses of the inplace
byteswapping functions *_to_cpus() and cpu_to_*s() with their
not-in-place equivalents. This is useful for where the swapping
is done on members of a packed struct -- taking the address
of the member to pass it to an inplace function is undefined
behaviour in C.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181009181612.10633-1-peter.maydell@linaro.org
---
scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++++++++++++++
1 file changed, 65 insertions(+)
create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
diff --git a/scripts/coccinelle/inplace-byteswaps.cocci b/scripts/coccinelle/inplace-byteswaps.cocci
new file mode 100644
index 00000000000..a869a90cbfd
--- /dev/null
+++ b/scripts/coccinelle/inplace-byteswaps.cocci
@@ -0,0 +1,65 @@
+// Replace uses of in-place byteswapping functions with calls to the
+// equivalent not-in-place functions. This is necessary to avoid
+// undefined behaviour if the expression being swapped is a field in a
+// packed struct.
+
+@@
+expression E;
+@@
+-be16_to_cpus(&E);
++E = be16_to_cpu(E);
+@@
+expression E;
+@@
+-be32_to_cpus(&E);
++E = be32_to_cpu(E);
+@@
+expression E;
+@@
+-be64_to_cpus(&E);
++E = be64_to_cpu(E);
+@@
+expression E;
+@@
+-cpu_to_be16s(&E);
++E = cpu_to_be16(E);
+@@
+expression E;
+@@
+-cpu_to_be32s(&E);
++E = cpu_to_be32(E);
+@@
+expression E;
+@@
+-cpu_to_be64s(&E);
++E = cpu_to_be64(E);
+@@
+expression E;
+@@
+-le16_to_cpus(&E);
++E = le16_to_cpu(E);
+@@
+expression E;
+@@
+-le32_to_cpus(&E);
++E = le32_to_cpu(E);
+@@
+expression E;
+@@
+-le64_to_cpus(&E);
++E = le64_to_cpu(E);
+@@
+expression E;
+@@
+-cpu_to_le16s(&E);
++E = cpu_to_le16(E);
+@@
+expression E;
+@@
+-cpu_to_le32s(&E);
++E = cpu_to_le32(E);
+@@
+expression E;
+@@
+-cpu_to_le64s(&E);
++E = cpu_to_le64(E);
--
2.19.0
prev parent reply other threads:[~2018-10-16 15:24 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-16 15:23 [Qemu-devel] [PULL 00/19] target-arm queue Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 01/19] hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 02/19] target/arm: Fix aarch64_sve_change_el wrt EL0 Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 03/19] target/arm: Define fields of ISAR registers Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 04/19] target/arm: Align cortex-r5 id_isar0 Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 05/19] target/arm: Fix cortex-a7 id_isar0 Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 06/19] net: cadence_gem: Disable TSU feature bit Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 07/19] net: cadence_gem: Announce availability of priority queues Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 08/19] net: cadence_gem: Use uint32_t for 32bit descriptor words Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 09/19] net: cadence_gem: Add macro with max number of " Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 10/19] net: cadence_gem: Add support for extended descriptors Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 11/19] net: cadence_gem: Add support for selecting the DMA MemoryRegion Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 12/19] net: cadence_gem: Implement support for 64bit descriptor addresses Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 13/19] net: cadence_gem: Announce 64bit addressing support Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 14/19] target-arm: powerctl: Enable HVC when starting CPUs to EL2 Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 15/19] target/arm: Add the Cortex-A72 Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 16/19] target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 17/19] target/arm: Mask PMOVSR writes based on supported counters Peter Maydell
2018-10-16 15:23 ` [Qemu-devel] [PULL 18/19] target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write Peter Maydell
2018-10-16 15:23 ` Peter Maydell [this message]
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