From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: qemu-devel@nongnu.org, qemu-arm@nongnu.org
Cc: peter.maydell@linaro.org, richard.henderson@linaro.org,
frederic.konrad@adacore.com, alistair@alistair23.me,
philmd@redhat.com, frasse.iglesias@gmail.com,
figlesia@xilinx.com, sstabellini@kernel.org,
sai.pavan.boddu@xilinx.com, edgar.iglesias@xilinx.com
Subject: [Qemu-devel] [PATCH v3 1/4] net: cadence_gem: Announce availability of priority queues
Date: Wed, 17 Oct 2018 23:39:29 +0200 [thread overview]
Message-ID: <20181017213932.19973-2-edgar.iglesias@gmail.com> (raw)
In-Reply-To: <20181017213932.19973-1-edgar.iglesias@gmail.com>
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Announce the availability of the various priority queues.
This fixes an issue where guest kernels would miss to
configure secondary queues due to inproper feature bits.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
hw/net/cadence_gem.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 1795998928..16a8455128 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1283,6 +1283,7 @@ static void gem_reset(DeviceState *d)
int i;
CadenceGEMState *s = CADENCE_GEM(d);
const uint8_t *a;
+ uint32_t queues_mask = 0;
DB_PRINT("\n");
@@ -1299,7 +1300,12 @@ static void gem_reset(DeviceState *d)
s->regs[GEM_DESCONF] = 0x02500111;
s->regs[GEM_DESCONF2] = 0x2ab13fff;
s->regs[GEM_DESCONF5] = 0x002f2045;
- s->regs[GEM_DESCONF6] = 0x00000200;
+ s->regs[GEM_DESCONF6] = 0x0;
+
+ if (s->num_priority_queues > 1) {
+ queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1);
+ s->regs[GEM_DESCONF6] |= queues_mask;
+ }
/* Set MAC address */
a = &s->conf.macaddr.a[0];
--
2.17.1
next prev parent reply other threads:[~2018-10-17 21:39 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-17 21:39 [Qemu-devel] [PATCH v3 0/4] arm: Add first models of Xilinx Versal SoC Edgar E. Iglesias
2018-10-17 21:39 ` Edgar E. Iglesias [this message]
2018-10-17 21:39 ` [Qemu-devel] [PATCH v3 2/4] net: cadence_gem: Announce 64bit addressing support Edgar E. Iglesias
2018-10-17 21:39 ` [Qemu-devel] [PATCH v3 3/4] hw/arm: versal: Add a model of Xilinx Versal SoC Edgar E. Iglesias
2018-10-19 14:18 ` Peter Maydell
2018-10-21 19:24 ` Edgar E. Iglesias
2018-10-21 21:25 ` Peter Maydell
2018-10-22 11:31 ` Edgar E. Iglesias
2018-10-17 21:39 ` [Qemu-devel] [PATCH v3 4/4] hw/arm: versal: Add a virtual Xilinx Versal board Edgar E. Iglesias
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