From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PATCH 1/3] target/arm: Remove writefn from TTBR0_EL3
Date: Thu, 18 Oct 2018 11:27:56 -0700 [thread overview]
Message-ID: <20181018182758.18646-2-richard.henderson@linaro.org> (raw)
In-Reply-To: <20181018182758.18646-1-richard.henderson@linaro.org>
The EL3 version of this register does not include an ASID,
and so the tlb_flush performed by vmsa_ttbr_write is not needed.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index e3946562aa..24bbde4f76 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4214,7 +4214,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
{ .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
- .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
+ .access = PL3_RW, .resetvalue = 0,
.fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
{ .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
--
2.17.2
next prev parent reply other threads:[~2018-10-18 18:28 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-18 18:27 [Qemu-devel] [PATCH 0/3] target/arm: Reduce tlb_flush overhead Richard Henderson
2018-10-18 18:27 ` Richard Henderson [this message]
2018-10-18 20:28 ` [Qemu-devel] [PATCH 1/3] target/arm: Remove writefn from TTBR0_EL3 Aaron Lindsay
2018-10-18 18:27 ` [Qemu-devel] [PATCH 2/3] target/arm: Only flush tlb if ASID changes Richard Henderson
2018-10-18 20:28 ` Aaron Lindsay
2018-10-18 18:27 ` [Qemu-devel] [PATCH 3/3] target/arm: Flush only the TLBs affected by TTBR*_EL1 Richard Henderson
2018-10-18 20:27 ` Aaron Lindsay
2018-10-18 20:52 ` Richard Henderson
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