From: Aaron Lindsay <Aaron@os.amperecomputing.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"peter.maydell@linaro.org" <peter.maydell@linaro.org>
Subject: Re: [Qemu-devel] [PATCH 3/3] target/arm: Flush only the TLBs affected by TTBR*_EL1
Date: Thu, 18 Oct 2018 20:27:27 +0000 [thread overview]
Message-ID: <20181018202719.GG12691@quinoa.localdomain> (raw)
In-Reply-To: <20181018182758.18646-4-richard.henderson@linaro.org>
On Oct 18 11:27, Richard Henderson wrote:
> @@ -2761,12 +2763,12 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
> .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
> { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
> .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
> - .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
> + .access = PL1_RW, .writefn = vmsa_ttbr1_write, .resetvalue = 0,
It's a little confusing that vmsa_ttbr1_write is used for TTBR0_EL1. Is
the '1' indicating the EL instead of which TTBR is being used?
-Aaron
next prev parent reply other threads:[~2018-10-18 20:27 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-18 18:27 [Qemu-devel] [PATCH 0/3] target/arm: Reduce tlb_flush overhead Richard Henderson
2018-10-18 18:27 ` [Qemu-devel] [PATCH 1/3] target/arm: Remove writefn from TTBR0_EL3 Richard Henderson
2018-10-18 20:28 ` Aaron Lindsay
2018-10-18 18:27 ` [Qemu-devel] [PATCH 2/3] target/arm: Only flush tlb if ASID changes Richard Henderson
2018-10-18 20:28 ` Aaron Lindsay
2018-10-18 18:27 ` [Qemu-devel] [PATCH 3/3] target/arm: Flush only the TLBs affected by TTBR*_EL1 Richard Henderson
2018-10-18 20:27 ` Aaron Lindsay [this message]
2018-10-18 20:52 ` Richard Henderson
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