From: Aaron Lindsay <Aaron@os.amperecomputing.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"peter.maydell@linaro.org" <peter.maydell@linaro.org>
Subject: Re: [Qemu-devel] [PATCH 1/3] target/arm: Remove writefn from TTBR0_EL3
Date: Thu, 18 Oct 2018 20:28:03 +0000 [thread overview]
Message-ID: <20181018202756.GH12691@quinoa.localdomain> (raw)
In-Reply-To: <20181018182758.18646-2-richard.henderson@linaro.org>
On Oct 18 11:27, Richard Henderson wrote:
> The EL3 version of this register does not include an ASID,
> and so the tlb_flush performed by vmsa_ttbr_write is not needed.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Aaron Lindsay <aaron@os.amperecomputing.com>
next prev parent reply other threads:[~2018-10-18 20:28 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-18 18:27 [Qemu-devel] [PATCH 0/3] target/arm: Reduce tlb_flush overhead Richard Henderson
2018-10-18 18:27 ` [Qemu-devel] [PATCH 1/3] target/arm: Remove writefn from TTBR0_EL3 Richard Henderson
2018-10-18 20:28 ` Aaron Lindsay [this message]
2018-10-18 18:27 ` [Qemu-devel] [PATCH 2/3] target/arm: Only flush tlb if ASID changes Richard Henderson
2018-10-18 20:28 ` Aaron Lindsay
2018-10-18 18:27 ` [Qemu-devel] [PATCH 3/3] target/arm: Flush only the TLBs affected by TTBR*_EL1 Richard Henderson
2018-10-18 20:27 ` Aaron Lindsay
2018-10-18 20:52 ` Richard Henderson
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