From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57566) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDK1m-0006Us-Ij for qemu-devel@nongnu.org; Thu, 18 Oct 2018 21:56:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gDK1j-0003y7-C9 for qemu-devel@nongnu.org; Thu, 18 Oct 2018 21:56:38 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:42196) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gDK1i-0003lc-Pt for qemu-devel@nongnu.org; Thu, 18 Oct 2018 21:56:35 -0400 Received: by mail-pl1-x641.google.com with SMTP id c8-v6so15121173plo.9 for ; Thu, 18 Oct 2018 18:56:24 -0700 (PDT) From: Richard Henderson Date: Thu, 18 Oct 2018 18:56:16 -0700 Message-Id: <20181019015617.22583-3-richard.henderson@linaro.org> In-Reply-To: <20181019015617.22583-1-richard.henderson@linaro.org> References: <20181019015617.22583-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH v2 2/3] target/arm: Only flush tlb if ASID changes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Since QEMU does not implement ASIDs, changes to the ASID must flush the tlb. However, if the ASID does not change there is no reason to flush. In testing a boot of the Ubuntu installer to the first menu, this reduces the number of flushes by 30%, or nearly 600k instances. Reviewed-by: Aaron Lindsay Signed-off-by: Richard Henderson --- target/arm/helper.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 24bbde4f76..ed70ac645e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2709,12 +2709,10 @@ static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* 64 bit accesses to the TTBRs can change the ASID and so we - * must flush the TLB. - */ - if (cpreg_field_is_64bit(ri)) { + /* If the ASID changes (with a 64-bit write), we must flush the TLB. */ + if (cpreg_field_is_64bit(ri) && + extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { ARMCPU *cpu = arm_env_get_cpu(env); - tlb_flush(CPU(cpu)); } raw_write(env, ri, value); -- 2.17.2