From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41050) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDlU0-0002T0-JF for qemu-devel@nongnu.org; Sat, 20 Oct 2018 03:15:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gDlTw-0004gI-3o for qemu-devel@nongnu.org; Sat, 20 Oct 2018 03:15:36 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:41644) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gDlTt-0004Ry-QE for qemu-devel@nongnu.org; Sat, 20 Oct 2018 03:15:30 -0400 From: Bastian Koppelmann Date: Sat, 20 Oct 2018 09:14:43 +0200 Message-Id: <20181020071451.27808-22-kbastian@mail.uni-paderborn.de> In-Reply-To: <20181020071451.27808-1-kbastian@mail.uni-paderborn.de> References: <20181020071451.27808-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v2 21/29] target/riscv: Remove manual decoding from gen_load() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: mjc@sifive.com, sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Cc: peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, richard.henderson@linaro.org, qemu-devel@nongnu.org With decodetree we don't need to convert RISC-V opcodes into to MemOps as the old gen_load() did. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- v1 -> v2: - trans_load -> gen_load - removed negative memop check target/riscv/insn_trans/trans_rvi.inc.c | 35 +++++++++++++++---------- target/riscv/translate.c | 20 -------------- 2 files changed, 21 insertions(+), 34 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index 411b4bfd42..77fa66b7cd 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -129,41 +129,49 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a, uint32_t insn) return gen_branch(ctx, a, TCG_COND_GEU); } +static bool gen_load(DisasContext *ctx, arg_lb *a, int memop) +{ + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + tcg_gen_addi_tl(t0, t0, a->imm); + + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop); + gen_set_gpr(a->rd, t1); + tcg_temp_free(t0); + tcg_temp_free(t1); + return true; +} + static bool trans_lb(DisasContext *ctx, arg_lb *a, uint32_t insn) { - gen_load(ctx, OPC_RISC_LB, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_SB); } static bool trans_lh(DisasContext *ctx, arg_lh *a, uint32_t insn) { - gen_load(ctx, OPC_RISC_LH, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_TESW); } static bool trans_lw(DisasContext *ctx, arg_lw *a, uint32_t insn) { - gen_load(ctx, OPC_RISC_LW, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_TESL); } static bool trans_lbu(DisasContext *ctx, arg_lbu *a, uint32_t insn) { - gen_load(ctx, OPC_RISC_LBU, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_UB); } static bool trans_lhu(DisasContext *ctx, arg_lhu *a, uint32_t insn) { - gen_load(ctx, OPC_RISC_LHU, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_TEUW); } static bool trans_lwu(DisasContext *ctx, arg_lwu *a, uint32_t insn) { #ifdef TARGET_RISCV64 - gen_load(ctx, OPC_RISC_LWU, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_TEUL); #else return false; #endif @@ -172,8 +180,7 @@ static bool trans_lwu(DisasContext *ctx, arg_lwu *a, uint32_t insn) static bool trans_ld(DisasContext *ctx, arg_ld *a, uint32_t insn) { #ifdef TARGET_RISCV64 - gen_load(ctx, OPC_RISC_LD, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_TEQ); #else return false; #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 52dbbd8ac8..947fb9345b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -489,26 +489,6 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd, ctx->base.is_jmp = DISAS_NORETURN; } -static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1, - target_long imm) -{ - TCGv t0 = tcg_temp_new(); - TCGv t1 = tcg_temp_new(); - gen_get_gpr(t0, rs1); - tcg_gen_addi_tl(t0, t0, imm); - int memop = tcg_memop_lookup[(opc >> 12) & 0x7]; - - if (memop < 0) { - gen_exception_illegal(ctx); - return; - } - - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop); - gen_set_gpr(rd, t1); - tcg_temp_free(t0); - tcg_temp_free(t1); -} - static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2, target_long imm) { -- 2.19.1