From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: mjc@sifive.com, sagark@eecs.berkeley.edu, palmer@sifive.com,
kbastian@mail.uni-paderborn.de
Cc: peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com,
richard.henderson@linaro.org, qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH v2 27/29] target/riscv: Remove gen_system()
Date: Sat, 20 Oct 2018 09:14:49 +0200 [thread overview]
Message-ID: <20181020071451.27808-28-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <20181020071451.27808-1-kbastian@mail.uni-paderborn.de>
with all 16 bit insns moved to decodetree no path is falling back to
gen_system(), so we can remove it.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/translate.c | 32 --------------------------------
1 file changed, 32 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b542daf844..a3b8792a1a 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -306,34 +306,6 @@ static void gen_set_rm(DisasContext *ctx, int rm)
tcg_temp_free_i32(t0);
}
-
-static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
- int rd, int rs1, int csr)
-{
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-
- switch (opc) {
- case OPC_RISC_ECALL:
- switch (csr) {
- case 0x0: /* ECALL */
- /* always generates U-level ECALL, fixed in do_interrupt handler */
- generate_exception(ctx, RISCV_EXCP_U_ECALL);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
- case 0x1: /* EBREAK */
- generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
- break;
- }
-}
-
#define EX_SH(amount) \
static int32_t ex_shift_##amount(int imm) \
{ \
@@ -458,10 +430,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
rd = GET_RD(ctx->opcode);
switch (op) {
- case OPC_RISC_SYSTEM:
- gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
- (ctx->opcode & 0xFFF00000) >> 20);
- break;
default:
gen_exception_illegal(ctx);
break;
--
2.19.1
next prev parent reply other threads:[~2018-10-20 7:15 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 01/29] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann
2018-10-25 16:38 ` Palmer Dabbelt
2018-10-25 16:54 ` Peter Maydell
2018-10-25 17:05 ` Palmer Dabbelt
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 02/29] targer/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
2018-10-20 19:32 ` Richard Henderson
2018-10-25 16:58 ` Palmer Dabbelt
2018-10-26 10:49 ` Bastian Koppelmann
2018-10-26 13:58 ` Richard Henderson
2018-10-26 14:53 ` Bastian Koppelmann
2018-10-26 15:42 ` Palmer Dabbelt
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 03/29] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
2018-10-20 19:34 ` Richard Henderson
2018-10-25 20:24 ` Palmer Dabbelt
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 04/29] target/riscv: Convert RVXI load/store " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 05/29] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 06/29] target/riscv: Convert RVXI fence " Bastian Koppelmann
2018-10-21 14:05 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 07/29] target/riscv: Convert RVXI csr " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 08/29] target/riscv: Convert RVXM " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 09/29] target/riscv: Convert RV32A " Bastian Koppelmann
2018-10-23 8:19 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 10/29] target/riscv: Convert RV64A " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 11/29] target/riscv: Convert RV32F " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 12/29] target/riscv: Convert RV64F " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 13/29] target/riscv: Convert RV32D " Bastian Koppelmann
2018-10-23 8:21 ` Richard Henderson
2018-10-31 10:44 ` Bastian Koppelmann
2018-10-31 10:47 ` Bastian Koppelmann
2018-10-31 17:21 ` Palmer Dabbelt
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 14/29] target/riscv: Convert RV64D " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 15/29] target/riscv: Convert RV priv " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 16/29] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
2018-10-23 8:31 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 17/29] target/riscv: Convert quadrant 1 " Bastian Koppelmann
2018-10-23 8:35 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 18/29] target/riscv: Convert quadrant 2 " Bastian Koppelmann
2018-10-23 8:39 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 19/29] target/riscv: Remove gen_jalr() Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 20/29] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 21/29] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 22/29] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
2018-10-23 8:46 ` Richard Henderson
2018-10-24 9:07 ` Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
2018-10-23 8:53 ` Richard Henderson
2018-10-23 8:55 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 25/29] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 26/29] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
2018-10-23 9:02 ` Richard Henderson
2018-10-20 7:14 ` Bastian Koppelmann [this message]
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 28/29] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
2018-10-23 9:04 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 29/29] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann
2018-10-23 9:04 ` Richard Henderson
2018-10-24 22:21 ` [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Palmer Dabbelt
2018-10-26 10:53 ` Bastian Koppelmann
2018-10-27 6:20 ` Palmer Dabbelt
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