* [Qemu-devel] [PATCH v3 1/3] hw/char: Implement nRF51 SoC UART
2018-10-25 0:50 [Qemu-devel] [PATCH v3 0/3] arm: Add nRF51 SoC UART support Julia Suvorova
@ 2018-10-25 0:50 ` Julia Suvorova
2018-10-25 0:50 ` [Qemu-devel] [PATCH v3 2/3] hw/arm/nrf51_soc: Connect UART to nRF51 SoC Julia Suvorova
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Julia Suvorova @ 2018-10-25 0:50 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Paolo Bonzini, Stefan Hajnoczi, Joel Stanley,
Jim Mussared, Steffen Görtz, Thomas Huth, Julia Suvorova
Not implemented: CTS/NCTS, PSEL*.
Signed-off-by: Julia Suvorova <jusual@mail.ru>
---
hw/char/Makefile.objs | 1 +
hw/char/nrf51_uart.c | 330 +++++++++++++++++++++++++++++++++++
hw/char/trace-events | 4 +
include/hw/char/nrf51_uart.h | 78 +++++++++
4 files changed, 413 insertions(+)
create mode 100644 hw/char/nrf51_uart.c
create mode 100644 include/hw/char/nrf51_uart.h
diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs
index b570531291..c4947d7ae7 100644
--- a/hw/char/Makefile.objs
+++ b/hw/char/Makefile.objs
@@ -1,5 +1,6 @@
common-obj-$(CONFIG_IPACK) += ipoctal232.o
common-obj-$(CONFIG_ESCC) += escc.o
+common-obj-$(CONFIG_NRF51_SOC) += nrf51_uart.o
common-obj-$(CONFIG_PARALLEL) += parallel.o
common-obj-$(CONFIG_PARALLEL) += parallel-isa.o
common-obj-$(CONFIG_PL011) += pl011.o
diff --git a/hw/char/nrf51_uart.c b/hw/char/nrf51_uart.c
new file mode 100644
index 0000000000..2f5fae6167
--- /dev/null
+++ b/hw/char/nrf51_uart.c
@@ -0,0 +1,330 @@
+/*
+ * nRF51 SoC UART emulation
+ *
+ * See nRF51 Series Reference Manual, "29 Universal Asynchronous
+ * Receiver/Transmitter" for hardware specifications:
+ * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
+ *
+ * Copyright (c) 2018 Julia Suvorova <jusual@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or
+ * (at your option) any later version.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "hw/char/nrf51_uart.h"
+#include "trace.h"
+
+static void nrf51_uart_update_irq(NRF51UARTState *s)
+{
+ bool irq = false;
+
+ irq |= (s->reg[R_UART_RXDRDY] &&
+ (s->reg[R_UART_INTEN] & R_UART_INTEN_RXDRDY_MASK));
+ irq |= (s->reg[R_UART_TXDRDY] &&
+ (s->reg[R_UART_INTEN] & R_UART_INTEN_TXDRDY_MASK));
+ irq |= (s->reg[R_UART_ERROR] &&
+ (s->reg[R_UART_INTEN] & R_UART_INTEN_ERROR_MASK));
+ irq |= (s->reg[R_UART_RXTO] &&
+ (s->reg[R_UART_INTEN] & R_UART_INTEN_RXTO_MASK));
+
+ qemu_set_irq(s->irq, irq);
+}
+
+static uint64_t uart_read(void *opaque, hwaddr addr, unsigned int size)
+{
+ NRF51UARTState *s = NRF51_UART(opaque);
+ uint64_t r;
+
+ if (!s->enabled) {
+ return 0;
+ }
+
+ switch (addr) {
+ case A_UART_RXD:
+ r = s->rx_fifo[s->rx_fifo_pos];
+ if (s->rx_started && s->rx_fifo_len) {
+ s->rx_fifo_pos = (s->rx_fifo_pos + 1) % UART_FIFO_LENGTH;
+ s->rx_fifo_len--;
+ if (s->rx_fifo_len) {
+ s->reg[R_UART_RXDRDY] = 1;
+ nrf51_uart_update_irq(s);
+ }
+ qemu_chr_fe_accept_input(&s->chr);
+ }
+ break;
+ case A_UART_INTENSET:
+ case A_UART_INTENCLR:
+ case A_UART_INTEN:
+ r = s->reg[R_UART_INTEN];
+ break;
+ default:
+ r = s->reg[addr / 4];
+ break;
+ }
+
+ trace_nrf51_uart_read(addr, r, size);
+
+ return r;
+}
+
+static gboolean uart_transmit(GIOChannel *chan, GIOCondition cond, void *opaque)
+{
+ NRF51UARTState *s = NRF51_UART(opaque);
+ int r;
+ uint8_t c = s->reg[R_UART_TXD];
+
+ s->watch_tag = 0;
+
+ r = qemu_chr_fe_write(&s->chr, &c, 1);
+ if (r <= 0) {
+ s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
+ uart_transmit, s);
+ if (!s->watch_tag) {
+ /* The hardware has no transmit error reporting,
+ * so silently drop the byte
+ */
+ goto buffer_drained;
+ }
+ return FALSE;
+ }
+
+buffer_drained:
+ s->reg[R_UART_TXDRDY] = 1;
+ s->pending_tx_byte = false;
+ return FALSE;
+}
+
+static void uart_cancel_transmit(NRF51UARTState *s)
+{
+ if (s->watch_tag) {
+ g_source_remove(s->watch_tag);
+ s->watch_tag = 0;
+ }
+}
+
+static void uart_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned int size)
+{
+ NRF51UARTState *s = NRF51_UART(opaque);
+
+ trace_nrf51_uart_write(addr, value, size);
+
+ if (!s->enabled && (addr != A_UART_ENABLE)) {
+ return;
+ }
+
+ switch (addr) {
+ case A_UART_TXD:
+ if (!s->pending_tx_byte && s->tx_started) {
+ s->reg[R_UART_TXD] = value;
+ s->pending_tx_byte = true;
+ uart_transmit(NULL, G_IO_OUT, s);
+ }
+ break;
+ case A_UART_INTEN:
+ s->reg[R_UART_INTEN] = value;
+ break;
+ case A_UART_INTENSET:
+ s->reg[R_UART_INTEN] |= value;
+ break;
+ case A_UART_INTENCLR:
+ s->reg[R_UART_INTEN] &= ~value;
+ break;
+ case A_UART_TXDRDY ... A_UART_RXTO:
+ s->reg[addr / 4] = value;
+ break;
+ case A_UART_ERRORSRC:
+ s->reg[addr / 4] &= ~value;
+ break;
+ case A_UART_RXD:
+ break;
+ case A_UART_RXDRDY:
+ if (value == 0) {
+ s->reg[R_UART_RXDRDY] = 0;
+ }
+ break;
+ case A_UART_STARTTX:
+ if (value == 1) {
+ s->tx_started = true;
+ }
+ break;
+ case A_UART_STARTRX:
+ if (value == 1) {
+ s->rx_started = true;
+ }
+ break;
+ case A_UART_ENABLE:
+ if (value) {
+ if (value == 4) {
+ s->enabled = true;
+ }
+ break;
+ }
+ s->enabled = false;
+ value = 1;
+ /* fall through */
+ case A_UART_SUSPEND:
+ case A_UART_STOPTX:
+ if (value == 1) {
+ s->tx_started = false;
+ }
+ /* fall through */
+ case A_UART_STOPRX:
+ if (addr != A_UART_STOPTX && value == 1) {
+ s->rx_started = false;
+ s->reg[R_UART_RXTO] = 1;
+ }
+ break;
+ default:
+ s->reg[addr / 4] = value;
+ break;
+ }
+ nrf51_uart_update_irq(s);
+}
+
+static const MemoryRegionOps uart_ops = {
+ .read = uart_read,
+ .write = uart_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void nrf51_uart_reset(DeviceState *dev)
+{
+ NRF51UARTState *s = NRF51_UART(dev);
+
+ s->pending_tx_byte = 0;
+
+ uart_cancel_transmit(s);
+
+ memset(s->reg, 0, sizeof(s->reg));
+
+ s->reg[R_UART_PSELRTS] = 0xFFFFFFFF;
+ s->reg[R_UART_PSELTXD] = 0xFFFFFFFF;
+ s->reg[R_UART_PSELCTS] = 0xFFFFFFFF;
+ s->reg[R_UART_PSELRXD] = 0xFFFFFFFF;
+ s->reg[R_UART_BAUDRATE] = 0x4000000;
+
+ s->rx_fifo_len = 0;
+ s->rx_fifo_pos = 0;
+ s->rx_started = false;
+ s->tx_started = false;
+ s->enabled = false;
+}
+
+static void uart_receive(void *opaque, const uint8_t *buf, int size)
+{
+
+ NRF51UARTState *s = NRF51_UART(opaque);
+ int i;
+
+ if (size == 0 || s->rx_fifo_len >= UART_FIFO_LENGTH) {
+ return;
+ }
+
+ for (i = 0; i < size; i++) {
+ uint32_t pos = (s->rx_fifo_pos + s->rx_fifo_len) % UART_FIFO_LENGTH;
+ s->rx_fifo[pos] = buf[i];
+ s->rx_fifo_len++;
+ }
+
+ s->reg[R_UART_RXDRDY] = 1;
+ nrf51_uart_update_irq(s);
+}
+
+static int uart_can_receive(void *opaque)
+{
+ NRF51UARTState *s = NRF51_UART(opaque);
+
+ return s->rx_started ? (UART_FIFO_LENGTH - s->rx_fifo_len) : 0;
+}
+
+static void uart_event(void *opaque, int event)
+{
+ NRF51UARTState *s = NRF51_UART(opaque);
+
+ if (event == CHR_EVENT_BREAK) {
+ s->reg[R_UART_ERRORSRC] |= 3;
+ s->reg[R_UART_ERROR] = 1;
+ nrf51_uart_update_irq(s);
+ }
+}
+
+static void nrf51_uart_realize(DeviceState *dev, Error **errp)
+{
+ NRF51UARTState *s = NRF51_UART(dev);
+
+ qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,
+ uart_event, NULL, s, NULL, true);
+}
+
+static void nrf51_uart_init(Object *obj)
+{
+ NRF51UARTState *s = NRF51_UART(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+
+ memory_region_init_io(&s->iomem, obj, &uart_ops, s,
+ "nrf51_soc.uart", UART_SIZE);
+ sysbus_init_mmio(sbd, &s->iomem);
+ sysbus_init_irq(sbd, &s->irq);
+}
+
+static int nrf51_uart_post_load(void *opaque, int version_id)
+{
+ NRF51UARTState *s = NRF51_UART(opaque);
+
+ if (s->pending_tx_byte) {
+ s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
+ uart_transmit, s);
+ }
+
+ return 0;
+}
+
+static const VMStateDescription nrf51_uart_vmstate = {
+ .name = "nrf51_soc.uart",
+ .post_load = nrf51_uart_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(reg, NRF51UARTState, 0x56C),
+ VMSTATE_UINT8_ARRAY(rx_fifo, NRF51UARTState, UART_FIFO_LENGTH),
+ VMSTATE_UINT32(rx_fifo_pos, NRF51UARTState),
+ VMSTATE_UINT32(rx_fifo_len, NRF51UARTState),
+ VMSTATE_BOOL(rx_started, NRF51UARTState),
+ VMSTATE_BOOL(tx_started, NRF51UARTState),
+ VMSTATE_BOOL(pending_tx_byte, NRF51UARTState),
+ VMSTATE_BOOL(enabled, NRF51UARTState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static Property nrf51_uart_properties[] = {
+ DEFINE_PROP_CHR("chardev", NRF51UARTState, chr),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void nrf51_uart_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = nrf51_uart_reset;
+ dc->realize = nrf51_uart_realize;
+ dc->props = nrf51_uart_properties;
+ dc->vmsd = &nrf51_uart_vmstate;
+}
+
+static const TypeInfo nrf51_uart_info = {
+ .name = TYPE_NRF51_UART,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(NRF51UARTState),
+ .instance_init = nrf51_uart_init,
+ .class_init = nrf51_uart_class_init
+};
+
+static void nrf51_uart_register_types(void)
+{
+ type_register_static(&nrf51_uart_info);
+}
+
+type_init(nrf51_uart_register_types)
diff --git a/hw/char/trace-events b/hw/char/trace-events
index b64213d4dd..de34a74399 100644
--- a/hw/char/trace-events
+++ b/hw/char/trace-events
@@ -73,3 +73,7 @@ cmsdk_apb_uart_receive(uint8_t c) "CMSDK APB UART: got character 0x%x from backe
cmsdk_apb_uart_tx_pending(void) "CMSDK APB UART: character send to backend pending"
cmsdk_apb_uart_tx(uint8_t c) "CMSDK APB UART: character 0x%x sent to backend"
cmsdk_apb_uart_set_params(int speed) "CMSDK APB UART: params set to %d 8N1"
+
+# hw/char/nrf51_uart.c
+nrf51_uart_read(uint64_t addr, uint64_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
+nrf51_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
diff --git a/include/hw/char/nrf51_uart.h b/include/hw/char/nrf51_uart.h
new file mode 100644
index 0000000000..e3ecb7c81c
--- /dev/null
+++ b/include/hw/char/nrf51_uart.h
@@ -0,0 +1,78 @@
+/*
+ * nRF51 SoC UART emulation
+ *
+ * Copyright (c) 2018 Julia Suvorova <jusual@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or
+ * (at your option) any later version.
+ */
+
+#ifndef NRF51_UART_H
+#define NRF51_UART_H
+
+#include "hw/sysbus.h"
+#include "chardev/char-fe.h"
+#include "hw/registerfields.h"
+
+#define UART_FIFO_LENGTH 6
+#define UART_BASE 0x40002000
+#define UART_SIZE 0x1000
+
+#define TYPE_NRF51_UART "nrf51_soc.uart"
+#define NRF51_UART(obj) OBJECT_CHECK(NRF51UARTState, (obj), TYPE_NRF51_UART)
+
+REG32(UART_STARTRX, 0x000)
+REG32(UART_STOPRX, 0x004)
+REG32(UART_STARTTX, 0x008)
+REG32(UART_STOPTX, 0x00C)
+REG32(UART_SUSPEND, 0x01C)
+
+REG32(UART_CTS, 0x100)
+REG32(UART_NCTS, 0x104)
+REG32(UART_RXDRDY, 0x108)
+REG32(UART_TXDRDY, 0x11C)
+REG32(UART_ERROR, 0x124)
+REG32(UART_RXTO, 0x144)
+
+REG32(UART_INTEN, 0x300)
+ FIELD(UART_INTEN, CTS, 0, 1)
+ FIELD(UART_INTEN, NCTS, 1, 1)
+ FIELD(UART_INTEN, RXDRDY, 2, 1)
+ FIELD(UART_INTEN, TXDRDY, 7, 1)
+ FIELD(UART_INTEN, ERROR, 9, 1)
+ FIELD(UART_INTEN, RXTO, 17, 1)
+REG32(UART_INTENSET, 0x304)
+REG32(UART_INTENCLR, 0x308)
+REG32(UART_ERRORSRC, 0x480)
+REG32(UART_ENABLE, 0x500)
+REG32(UART_PSELRTS, 0x508)
+REG32(UART_PSELTXD, 0x50C)
+REG32(UART_PSELCTS, 0x510)
+REG32(UART_PSELRXD, 0x514)
+REG32(UART_RXD, 0x518)
+REG32(UART_TXD, 0x51C)
+REG32(UART_BAUDRATE, 0x524)
+REG32(UART_CONFIG, 0x56C)
+
+typedef struct NRF51UARTState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+ CharBackend chr;
+ qemu_irq irq;
+ guint watch_tag;
+
+ uint8_t rx_fifo[UART_FIFO_LENGTH];
+ unsigned int rx_fifo_pos;
+ unsigned int rx_fifo_len;
+
+ uint32_t reg[0x56C];
+
+ bool rx_started;
+ bool tx_started;
+ bool pending_tx_byte;
+ bool enabled;
+} NRF51UARTState;
+
+#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [Qemu-devel] [PATCH v3 2/3] hw/arm/nrf51_soc: Connect UART to nRF51 SoC
2018-10-25 0:50 [Qemu-devel] [PATCH v3 0/3] arm: Add nRF51 SoC UART support Julia Suvorova
2018-10-25 0:50 ` [Qemu-devel] [PATCH v3 1/3] hw/char: Implement nRF51 SoC UART Julia Suvorova
@ 2018-10-25 0:50 ` Julia Suvorova
2018-10-25 9:25 ` Alistair Francis
2018-10-25 0:50 ` [Qemu-devel] [PATCH v3 3/3] tests/boot-serial-test: Add microbit board testcase Julia Suvorova
` (2 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Julia Suvorova @ 2018-10-25 0:50 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Paolo Bonzini, Stefan Hajnoczi, Joel Stanley,
Jim Mussared, Steffen Görtz, Thomas Huth, Julia Suvorova
Wire up nRF51 UART in the corresponding SoC.
Signed-off-by: Julia Suvorova <jusual@mail.ru>
---
hw/arm/microbit.c | 2 ++
hw/arm/nrf51_soc.c | 20 ++++++++++++++++++++
include/hw/arm/nrf51_soc.h | 3 +++
3 files changed, 25 insertions(+)
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
index e7d74116a5..a734e7f650 100644
--- a/hw/arm/microbit.c
+++ b/hw/arm/microbit.c
@@ -12,6 +12,7 @@
#include "qapi/error.h"
#include "hw/boards.h"
#include "hw/arm/arm.h"
+#include "sysemu/sysemu.h"
#include "exec/address-spaces.h"
#include "hw/arm/nrf51_soc.h"
@@ -35,6 +36,7 @@ static void microbit_init(MachineState *machine)
sysbus_init_child_obj(OBJECT(machine), "nrf51", soc, sizeof(s->nrf51),
TYPE_NRF51_SOC);
+ qdev_prop_set_chr(DEVICE(&s->nrf51), "serial0", serial_hd(0));
object_property_set_link(soc, OBJECT(system_memory), "memory",
&error_fatal);
object_property_set_bool(soc, true, "realized", &error_fatal);
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
index 1a59ef4552..b89c1bdea0 100644
--- a/hw/arm/nrf51_soc.c
+++ b/hw/arm/nrf51_soc.c
@@ -43,9 +43,12 @@
#define NRF51822_FLASH_SIZE (256 * 1024)
#define NRF51822_SRAM_SIZE (16 * 1024)
+#define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)
+
static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
{
NRF51State *s = NRF51_SOC(dev_soc);
+ MemoryRegion *mr;
Error *err = NULL;
if (!s->board_memory) {
@@ -82,6 +85,18 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
}
memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram);
+ /* UART */
+ object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);
+ memory_region_add_subregion_overlap(&s->container, UART_BASE, mr, 0);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,
+ qdev_get_gpio_in(DEVICE(&s->cpu),
+ BASE_TO_IRQ(UART_BASE)));
+
create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE);
create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE);
create_unimplemented_device("nrf51_soc.private",
@@ -99,6 +114,11 @@ static void nrf51_soc_init(Object *obj)
qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
ARM_CPU_TYPE_NAME("cortex-m0"));
qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
+
+ sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart),
+ TYPE_NRF51_UART);
+ object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev",
+ &error_abort);
}
static Property nrf51_soc_properties[] = {
diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h
index f4e092b554..73fc92e9a8 100644
--- a/include/hw/arm/nrf51_soc.h
+++ b/include/hw/arm/nrf51_soc.h
@@ -12,6 +12,7 @@
#include "hw/sysbus.h"
#include "hw/arm/armv7m.h"
+#include "hw/char/nrf51_uart.h"
#define TYPE_NRF51_SOC "nrf51-soc"
#define NRF51_SOC(obj) \
@@ -24,6 +25,8 @@ typedef struct NRF51State {
/*< public >*/
ARMv7MState cpu;
+ NRF51UARTState uart;
+
MemoryRegion iomem;
MemoryRegion sram;
MemoryRegion flash;
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [Qemu-devel] [PATCH v3 2/3] hw/arm/nrf51_soc: Connect UART to nRF51 SoC
2018-10-25 0:50 ` [Qemu-devel] [PATCH v3 2/3] hw/arm/nrf51_soc: Connect UART to nRF51 SoC Julia Suvorova
@ 2018-10-25 9:25 ` Alistair Francis
0 siblings, 0 replies; 8+ messages in thread
From: Alistair Francis @ 2018-10-25 9:25 UTC (permalink / raw)
To: Julia Suvorova
Cc: qemu-devel@nongnu.org Developers, Peter Maydell, Jim Mussared,
mail, Thomas Huth, Joel Stanley, Stefan Hajnoczi, Paolo Bonzini
On Thu, Oct 25, 2018 at 1:56 AM Julia Suvorova via Qemu-devel
<qemu-devel@nongnu.org> wrote:
>
> Wire up nRF51 UART in the corresponding SoC.
>
> Signed-off-by: Julia Suvorova <jusual@mail.ru>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/arm/microbit.c | 2 ++
> hw/arm/nrf51_soc.c | 20 ++++++++++++++++++++
> include/hw/arm/nrf51_soc.h | 3 +++
> 3 files changed, 25 insertions(+)
>
> diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
> index e7d74116a5..a734e7f650 100644
> --- a/hw/arm/microbit.c
> +++ b/hw/arm/microbit.c
> @@ -12,6 +12,7 @@
> #include "qapi/error.h"
> #include "hw/boards.h"
> #include "hw/arm/arm.h"
> +#include "sysemu/sysemu.h"
> #include "exec/address-spaces.h"
>
> #include "hw/arm/nrf51_soc.h"
> @@ -35,6 +36,7 @@ static void microbit_init(MachineState *machine)
>
> sysbus_init_child_obj(OBJECT(machine), "nrf51", soc, sizeof(s->nrf51),
> TYPE_NRF51_SOC);
> + qdev_prop_set_chr(DEVICE(&s->nrf51), "serial0", serial_hd(0));
> object_property_set_link(soc, OBJECT(system_memory), "memory",
> &error_fatal);
> object_property_set_bool(soc, true, "realized", &error_fatal);
> diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
> index 1a59ef4552..b89c1bdea0 100644
> --- a/hw/arm/nrf51_soc.c
> +++ b/hw/arm/nrf51_soc.c
> @@ -43,9 +43,12 @@
> #define NRF51822_FLASH_SIZE (256 * 1024)
> #define NRF51822_SRAM_SIZE (16 * 1024)
>
> +#define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)
> +
> static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
> {
> NRF51State *s = NRF51_SOC(dev_soc);
> + MemoryRegion *mr;
> Error *err = NULL;
>
> if (!s->board_memory) {
> @@ -82,6 +85,18 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
> }
> memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram);
>
> + /* UART */
> + object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);
> + memory_region_add_subregion_overlap(&s->container, UART_BASE, mr, 0);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,
> + qdev_get_gpio_in(DEVICE(&s->cpu),
> + BASE_TO_IRQ(UART_BASE)));
> +
> create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE);
> create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE);
> create_unimplemented_device("nrf51_soc.private",
> @@ -99,6 +114,11 @@ static void nrf51_soc_init(Object *obj)
> qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
> ARM_CPU_TYPE_NAME("cortex-m0"));
> qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
> +
> + sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart),
> + TYPE_NRF51_UART);
> + object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev",
> + &error_abort);
> }
>
> static Property nrf51_soc_properties[] = {
> diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h
> index f4e092b554..73fc92e9a8 100644
> --- a/include/hw/arm/nrf51_soc.h
> +++ b/include/hw/arm/nrf51_soc.h
> @@ -12,6 +12,7 @@
>
> #include "hw/sysbus.h"
> #include "hw/arm/armv7m.h"
> +#include "hw/char/nrf51_uart.h"
>
> #define TYPE_NRF51_SOC "nrf51-soc"
> #define NRF51_SOC(obj) \
> @@ -24,6 +25,8 @@ typedef struct NRF51State {
> /*< public >*/
> ARMv7MState cpu;
>
> + NRF51UARTState uart;
> +
> MemoryRegion iomem;
> MemoryRegion sram;
> MemoryRegion flash;
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Qemu-devel] [PATCH v3 3/3] tests/boot-serial-test: Add microbit board testcase
2018-10-25 0:50 [Qemu-devel] [PATCH v3 0/3] arm: Add nRF51 SoC UART support Julia Suvorova
2018-10-25 0:50 ` [Qemu-devel] [PATCH v3 1/3] hw/char: Implement nRF51 SoC UART Julia Suvorova
2018-10-25 0:50 ` [Qemu-devel] [PATCH v3 2/3] hw/arm/nrf51_soc: Connect UART to nRF51 SoC Julia Suvorova
@ 2018-10-25 0:50 ` Julia Suvorova
2018-10-25 8:36 ` [Qemu-devel] [PATCH v3 0/3] arm: Add nRF51 SoC UART support Stefan Hajnoczi
2018-10-29 14:37 ` Peter Maydell
4 siblings, 0 replies; 8+ messages in thread
From: Julia Suvorova @ 2018-10-25 0:50 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Paolo Bonzini, Stefan Hajnoczi, Joel Stanley,
Jim Mussared, Steffen Görtz, Thomas Huth, Julia Suvorova
New mini-kernel test for nRF51 SoC UART.
Signed-off-by: Julia Suvorova <jusual@mail.ru>
Acked-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
---
tests/boot-serial-test.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c
index f865822e32..8ec6aed35d 100644
--- a/tests/boot-serial-test.c
+++ b/tests/boot-serial-test.c
@@ -62,6 +62,24 @@ static const uint8_t kernel_aarch64[] = {
0xfd, 0xff, 0xff, 0x17, /* b -12 (loop) */
};
+static const uint8_t kernel_nrf51[] = {
+ 0x00, 0x00, 0x00, 0x00, /* Stack top address */
+ 0x09, 0x00, 0x00, 0x00, /* Reset handler address */
+ 0x04, 0x4a, /* ldr r2, [pc, #16] Get ENABLE */
+ 0x04, 0x21, /* movs r1, #4 */
+ 0x11, 0x60, /* str r1, [r2] */
+ 0x04, 0x4a, /* ldr r2, [pc, #16] Get STARTTX */
+ 0x01, 0x21, /* movs r1, #1 */
+ 0x11, 0x60, /* str r1, [r2] */
+ 0x03, 0x4a, /* ldr r2, [pc, #12] Get TXD */
+ 0x54, 0x21, /* movs r1, 'T' */
+ 0x11, 0x60, /* str r1, [r2] */
+ 0xfe, 0xe7, /* b . */
+ 0x00, 0x25, 0x00, 0x40, /* 0x40002500 = UART ENABLE */
+ 0x08, 0x20, 0x00, 0x40, /* 0x40002008 = UART STARTTX */
+ 0x1c, 0x25, 0x00, 0x40 /* 0x4000251c = UART TXD */
+};
+
typedef struct testdef {
const char *arch; /* Target architecture */
const char *machine; /* Name of the machine */
@@ -105,6 +123,7 @@ static testdef_t tests[] = {
{ "hppa", "hppa", "", "SeaBIOS wants SYSTEM HALT" },
{ "aarch64", "virt", "-cpu cortex-a57", "TT", sizeof(kernel_aarch64),
kernel_aarch64 },
+ { "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 },
{ NULL }
};
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [Qemu-devel] [PATCH v3 0/3] arm: Add nRF51 SoC UART support
2018-10-25 0:50 [Qemu-devel] [PATCH v3 0/3] arm: Add nRF51 SoC UART support Julia Suvorova
` (2 preceding siblings ...)
2018-10-25 0:50 ` [Qemu-devel] [PATCH v3 3/3] tests/boot-serial-test: Add microbit board testcase Julia Suvorova
@ 2018-10-25 8:36 ` Stefan Hajnoczi
2018-10-29 14:37 ` Peter Maydell
4 siblings, 0 replies; 8+ messages in thread
From: Stefan Hajnoczi @ 2018-10-25 8:36 UTC (permalink / raw)
To: Julia Suvorova
Cc: qemu-devel, Peter Maydell, Jim Mussared, Steffen Görtz,
Thomas Huth, Joel Stanley, Stefan Hajnoczi, Paolo Bonzini
[-- Attachment #1: Type: text/plain, Size: 1452 bytes --]
On Thu, Oct 25, 2018 at 03:50:49AM +0300, Julia Suvorova via Qemu-devel wrote:
> This series adds support for the nRF51 SoC UART, that used in
> BBC Micro:bit board, and QTest for it.
>
> v3:
> * serial_hd() moved to the board code
> * sysbus_init_child_obj() used for initialization
> * qemu_chr_fe_accept_input() called after byte popping
>
> v2:
> * Suspend/Enable functionality added
> * Connection to SoC moved to a separate patch
> * Added QTest for checking reception functionality
> * Mini-kernel test changed to fit current implementation
> * Addressed review comments on R_*, uart_can_receive, VMState,
> uart_transmit
>
> Julia Suvorova (3):
> hw/char: Implement nRF51 SoC UART
> hw/arm/nrf51_soc: Connect UART to nRF51 SoC
> tests/boot-serial-test: Add microbit board testcase
>
> hw/arm/microbit.c | 2 +
> hw/arm/nrf51_soc.c | 20 +++
> hw/char/Makefile.objs | 1 +
> hw/char/nrf51_uart.c | 330 +++++++++++++++++++++++++++++++++++
> hw/char/trace-events | 4 +
> include/hw/arm/nrf51_soc.h | 3 +
> include/hw/char/nrf51_uart.h | 78 +++++++++
> tests/boot-serial-test.c | 19 ++
> 8 files changed, 457 insertions(+)
> create mode 100644 hw/char/nrf51_uart.c
> create mode 100644 include/hw/char/nrf51_uart.h
>
> --
> 2.17.1
>
>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
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^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [Qemu-devel] [PATCH v3 0/3] arm: Add nRF51 SoC UART support
2018-10-25 0:50 [Qemu-devel] [PATCH v3 0/3] arm: Add nRF51 SoC UART support Julia Suvorova
` (3 preceding siblings ...)
2018-10-25 8:36 ` [Qemu-devel] [PATCH v3 0/3] arm: Add nRF51 SoC UART support Stefan Hajnoczi
@ 2018-10-29 14:37 ` Peter Maydell
2018-11-01 10:19 ` Stefan Hajnoczi
4 siblings, 1 reply; 8+ messages in thread
From: Peter Maydell @ 2018-10-29 14:37 UTC (permalink / raw)
To: Julia Suvorova
Cc: QEMU Developers, Paolo Bonzini, Stefan Hajnoczi, Joel Stanley,
Jim Mussared, Steffen Görtz, Thomas Huth
On 25 October 2018 at 01:50, Julia Suvorova <jusual@mail.ru> wrote:
> This series adds support for the nRF51 SoC UART, that used in
> BBC Micro:bit board, and QTest for it.
>
> v3:
> * serial_hd() moved to the board code
> * sysbus_init_child_obj() used for initialization
> * qemu_chr_fe_accept_input() called after byte popping
>
> v2:
> * Suspend/Enable functionality added
> * Connection to SoC moved to a separate patch
> * Added QTest for checking reception functionality
> * Mini-kernel test changed to fit current implementation
> * Addressed review comments on R_*, uart_can_receive, VMState,
> uart_transmit
>
> Julia Suvorova (3):
> hw/char: Implement nRF51 SoC UART
> hw/arm/nrf51_soc: Connect UART to nRF51 SoC
> tests/boot-serial-test: Add microbit board testcase
Applied to target-arm.next, thanks.
What's the current status of the 'microbit' board with these
patches? Are we missing anything important? Can we run any
interesting guest programs?
thanks
-- PMM
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [Qemu-devel] [PATCH v3 0/3] arm: Add nRF51 SoC UART support
2018-10-29 14:37 ` Peter Maydell
@ 2018-11-01 10:19 ` Stefan Hajnoczi
0 siblings, 0 replies; 8+ messages in thread
From: Stefan Hajnoczi @ 2018-11-01 10:19 UTC (permalink / raw)
To: Peter Maydell
Cc: Julia Suvorova, Jim Mussared, Steffen Görtz, QEMU Developers,
Joel Stanley, Stefan Hajnoczi, Thomas Huth, Paolo Bonzini
[-- Attachment #1: Type: text/plain, Size: 1509 bytes --]
On Mon, Oct 29, 2018 at 02:37:42PM +0000, Peter Maydell wrote:
> On 25 October 2018 at 01:50, Julia Suvorova <jusual@mail.ru> wrote:
> > This series adds support for the nRF51 SoC UART, that used in
> > BBC Micro:bit board, and QTest for it.
> >
> > v3:
> > * serial_hd() moved to the board code
> > * sysbus_init_child_obj() used for initialization
> > * qemu_chr_fe_accept_input() called after byte popping
> >
> > v2:
> > * Suspend/Enable functionality added
> > * Connection to SoC moved to a separate patch
> > * Added QTest for checking reception functionality
> > * Mini-kernel test changed to fit current implementation
> > * Addressed review comments on R_*, uart_can_receive, VMState,
> > uart_transmit
> >
> > Julia Suvorova (3):
> > hw/char: Implement nRF51 SoC UART
> > hw/arm/nrf51_soc: Connect UART to nRF51 SoC
> > tests/boot-serial-test: Add microbit board testcase
>
> Applied to target-arm.next, thanks.
>
> What's the current status of the 'microbit' board with these
> patches? Are we missing anything important? Can we run any
> interesting guest programs?
qemu.git/master can't run interesting programs yet. Missing:
* Steffen Görtz's patches (rng, timer, uicr, ficr)
* Julia's serial qtest (this is a prerequisite for the next item)
* My -kernel vs -device loader fix (currently qemu.git/master is broken
and cannot load any kernel at all!)
But we're getting there step by step :).
Stefan
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^ permalink raw reply [flat|nested] 8+ messages in thread