[Qemu-devel] [PATCH 0/4] target/arm: Minimize TLB flushing for ASID changes

[Richard Henderson <richard.henderson@linaro.org>]

In http://lists.nongnu.org/archive/html/qemu-devel/2018-10/msg04181.html
(already upstream) I added a check for ASID changes without realizing
that TTBCR_EL1 has the A1 bit, controlling which register actually
contains the active ASID.

In http://lists.nongnu.org/archive/html/qemu-devel/2018-10/msg04182.html
I suggested a set of mmu_idx to flush when the ASID does change.  In
follow-up, Peter suggested more.

I now choose secure vs non-secure mmu_idx based on which register is being
modified, not the current state of the cpu.  Unless I am mistaken, secure
state can write to the non-secure registers.  Which means that the current
state of the cpu is irrelevant and only the register matters.

Peter suggested flushing S1E3 when changing ttbr0_s.  I can see how this
is overlapped onto the EL3 (Secure Monitor) state, but I cannot see how
the ASID is used from EL3.  The best evidence I can find for this is that
there is no TLBIASID* register that is applicable to flushing EL3; that's
not conclusive proof though.  So while I'm not sure it's necessary, I'm
also not sure it isn't necessary, and so I've included S1E3 in the flush.

I now also use the VMID to conditionally invalidate the stage 2 translation
state.  This shows how I anticipaged @depmap to be used in patch 1.


r~


Richard Henderson (4):
  cputlb: Add tlb_set_asid_for_mmuidx
  target/arm: Install ASIDs for long-form from EL1
  target/arm: Install ASIDs for short-form from EL1
  target/arm: Install ASIDs for EL2

 include/exec/cpu-defs.h |   2 +
 include/exec/exec-all.h |  19 ++++++
 accel/tcg/cputlb.c      |  23 +++++++
 target/arm/helper.c     | 133 ++++++++++++++++++++++++++--------------
 4 files changed, 131 insertions(+), 46 deletions(-)

-- 
2.17.2