From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37894) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHSVu-0001Ls-Kw for qemu-devel@nongnu.org; Tue, 30 Oct 2018 07:48:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gHSVq-0001jo-ON for qemu-devel@nongnu.org; Tue, 30 Oct 2018 07:48:50 -0400 Received: from mx1.redhat.com ([209.132.183.28]:34666) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gHSVn-0001ca-18 for qemu-devel@nongnu.org; Tue, 30 Oct 2018 07:48:43 -0400 From: P J P Date: Tue, 30 Oct 2018 17:16:35 +0530 Message-Id: <20181030114635.31232-1-ppandit@redhat.com> Subject: [Qemu-devel] [PATCH v3] strongarm: mask off high[31:28] bits from dir and state registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Qemu Developers Cc: Peter Maydell , Moguofang , liqsub1 , Prasad J Pandit From: Prasad J Pandit The high[31:28] bits of 'direction' and 'state' registers of SA-1100/SA-1110 device are reserved. Setting them may lead to OOB 's->handler[]' array access issue. Mask off [31:28] bits to avoid it. Reported-by: Moguofang Signed-off-by: Prasad J Pandit --- hw/arm/strongarm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Update v3: fix the mask value to 0x0fffffff -> https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg06088.html diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index ec2627374d..644a9c45b4 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -587,12 +587,12 @@ static void strongarm_gpio_write(void *opaque, hwaddr offset, switch (offset) { case GPDR: /* GPIO Pin-Direction registers */ - s->dir = value; + s->dir = value & 0x0fffffff; strongarm_gpio_handler_update(s); break; case GPSR: /* GPIO Pin-Output Set registers */ - s->olevel |= value; + s->olevel |= value & 0x0fffffff; strongarm_gpio_handler_update(s); break; -- 2.17.2