From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: mjc@sifive.com, sagark@eecs.berkeley.edu, palmer@sifive.com,
kbastian@mail.uni-paderborn.de, Alistair.Francis@wdc.com
Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [Qemu-devel] [PATCH v3 28/35] target/riscv: Rename trans_arith to gen_arith
Date: Wed, 31 Oct 2018 14:20:22 +0100 [thread overview]
Message-ID: <20181031132029.4887-29-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <20181031132029.4887-1-kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/riscv/insn_trans/trans_rvi.inc.c | 14 +++++++-------
target/riscv/insn_trans/trans_rvm.inc.c | 14 +++++++-------
target/riscv/translate.c | 4 ++--
3 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 65548d1281..227742232c 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -301,12 +301,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a)
static bool trans_add(DisasContext *ctx, arg_add *a)
{
- return trans_arith(ctx, a, &tcg_gen_add_tl);
+ return gen_arith(ctx, a, &tcg_gen_add_tl);
}
static bool trans_sub(DisasContext *ctx, arg_sub *a)
{
- return trans_arith(ctx, a, &tcg_gen_sub_tl);
+ return gen_arith(ctx, a, &tcg_gen_sub_tl);
}
static bool trans_sll(DisasContext *ctx, arg_sll *a)
@@ -348,7 +348,7 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
static bool trans_xor(DisasContext *ctx, arg_xor *a)
{
- return trans_arith(ctx, a, &tcg_gen_xor_tl);
+ return gen_arith(ctx, a, &tcg_gen_xor_tl);
}
static bool trans_srl(DisasContext *ctx, arg_srl *a)
@@ -363,12 +363,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
static bool trans_or(DisasContext *ctx, arg_or *a)
{
- return trans_arith(ctx, a, &tcg_gen_or_tl);
+ return gen_arith(ctx, a, &tcg_gen_or_tl);
}
static bool trans_and(DisasContext *ctx, arg_and *a)
{
- return trans_arith(ctx, a, &tcg_gen_and_tl);
+ return gen_arith(ctx, a, &tcg_gen_and_tl);
}
#ifdef TARGET_RISCV64
@@ -417,12 +417,12 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
static bool trans_addw(DisasContext *ctx, arg_addw *a)
{
- return trans_arith(ctx, a, &tcg_gen_add_tl);
+ return gen_arith(ctx, a, &tcg_gen_add_tl);
}
static bool trans_subw(DisasContext *ctx, arg_subw *a)
{
- return trans_arith(ctx, a, &tcg_gen_sub_tl);
+ return gen_arith(ctx, a, &tcg_gen_sub_tl);
}
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_trans/trans_rvm.inc.c
index 949f59ddb2..5844d6f5be 100644
--- a/target/riscv/insn_trans/trans_rvm.inc.c
+++ b/target/riscv/insn_trans/trans_rvm.inc.c
@@ -21,7 +21,7 @@
static bool trans_mul(DisasContext *ctx, arg_mul *a)
{
- return trans_arith(ctx, a, &tcg_gen_mul_tl);
+ return gen_arith(ctx, a, &tcg_gen_mul_tl);
}
static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
@@ -41,7 +41,7 @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
{
- return trans_arith(ctx, a, &gen_mulhsu);
+ return gen_arith(ctx, a, &gen_mulhsu);
}
static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
@@ -61,28 +61,28 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
static bool trans_div(DisasContext *ctx, arg_div *a)
{
- return trans_arith(ctx, a, &gen_div);
+ return gen_arith(ctx, a, &gen_div);
}
static bool trans_divu(DisasContext *ctx, arg_divu *a)
{
- return trans_arith(ctx, a, &gen_divu);
+ return gen_arith(ctx, a, &gen_divu);
}
static bool trans_rem(DisasContext *ctx, arg_rem *a)
{
- return trans_arith(ctx, a, &gen_rem);
+ return gen_arith(ctx, a, &gen_rem);
}
static bool trans_remu(DisasContext *ctx, arg_remu *a)
{
- return trans_arith(ctx, a, &gen_remu);
+ return gen_arith(ctx, a, &gen_remu);
}
#ifdef TARGET_RISCV64
static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
{
- return trans_arith(ctx, a, &gen_mulw);
+ return gen_arith(ctx, a, &gen_mulw);
}
static bool trans_divw(DisasContext *ctx, arg_divw *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index fd4b63b4c4..68223925ba 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -569,8 +569,8 @@ static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
}
#endif
-static bool trans_arith(DisasContext *ctx, arg_r *a,
- void(*func)(TCGv, TCGv, TCGv))
+static bool gen_arith(DisasContext *ctx, arg_r *a,
+ void(*func)(TCGv, TCGv, TCGv))
{
TCGv source1, source2;
source1 = tcg_temp_new();
--
2.19.1
next prev parent reply other threads:[~2018-10-31 13:22 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-31 13:19 [Qemu-devel] [PATCH v3 00/35] target/riscv: Convert to decodetree Bastian Koppelmann
2018-10-31 13:19 ` [Qemu-devel] [PATCH v3 01/35] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann
2018-10-31 17:07 ` Richard Henderson
2018-10-31 20:14 ` Alistair Francis
2018-10-31 13:19 ` [Qemu-devel] [PATCH v3 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
2018-10-31 20:20 ` Alistair
2018-10-31 13:19 ` [Qemu-devel] [PATCH v3 03/35] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
2018-10-31 17:11 ` Richard Henderson
2018-10-31 13:19 ` [Qemu-devel] [PATCH v3 04/35] target/riscv: Convert RV32I load/store " Bastian Koppelmann
2018-10-31 13:19 ` [Qemu-devel] [PATCH v3 05/35] target/riscv: Convert RV64I " Bastian Koppelmann
2018-10-31 17:14 ` Richard Henderson
2018-10-31 20:26 ` Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 06/35] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
2018-10-31 17:15 ` Richard Henderson
2018-10-31 20:29 ` Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 07/35] target/riscv: Convert RVXI fence " Bastian Koppelmann
2018-10-31 20:30 ` Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 08/35] target/riscv: Convert RVXI csr " Bastian Koppelmann
2018-10-31 20:46 ` Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 09/35] target/riscv: Convert RVXM " Bastian Koppelmann
2018-10-31 20:38 ` Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 10/35] target/riscv: Convert RV32A " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 11/35] target/riscv: Convert RV64A " Bastian Koppelmann
2018-10-31 20:49 ` Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 12/35] target/riscv: Convert RV32F " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 13/35] target/riscv: Convert RV64F " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 14/35] target/riscv: Convert RV32D " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 15/35] target/riscv: Convert RV64D " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 16/35] target/riscv: Convert RV priv " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 17/35] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 18/35] target/riscv: Convert quadrant 1 " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 19/35] target/riscv: Convert quadrant 2 " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 20/35] target/riscv: Remove gen_jalr() Bastian Koppelmann
2018-10-31 20:50 ` Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 21/35] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 22/35] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann
2018-10-31 22:09 ` Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 23/35] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann
2018-10-31 22:09 ` Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
2018-10-31 22:18 ` Richard Henderson
2019-01-11 13:10 ` Bastian Koppelmann
2019-01-11 21:00 ` Richard Henderson
2019-01-18 12:00 ` Bastian Koppelmann
2018-10-31 22:26 ` Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
2018-10-31 20:44 ` Alistair Francis
2018-10-31 22:27 ` Richard Henderson
2018-10-31 22:26 ` Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 26/35] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann
2018-10-31 22:38 ` Richard Henderson
2018-11-01 15:59 ` Palmer Dabbelt
2018-11-05 17:00 ` Bastian Koppelmann
2018-11-07 0:56 ` Palmer Dabbelt
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 27/35] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
2018-10-31 22:39 ` Richard Henderson
2018-10-31 13:20 ` Bastian Koppelmann [this message]
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 29/35] target/riscv: Remove gen_system() Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 30/35] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 31/35] target/riscv: Convert @cs_2 insns to share translation functions Bastian Koppelmann
2018-10-31 22:42 ` Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann
2018-10-31 22:43 ` Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann
2018-10-31 22:45 ` Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 34/35] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann
2018-10-31 22:47 ` Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann
2018-10-31 22:49 ` Richard Henderson
2018-11-02 8:48 ` [Qemu-devel] [PATCH v3 00/35] target/riscv: Convert to decodetree no-reply
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