From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37751) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHqRj-0004wU-Dj for qemu-devel@nongnu.org; Wed, 31 Oct 2018 09:22:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gHqRi-0003G7-CI for qemu-devel@nongnu.org; Wed, 31 Oct 2018 09:22:07 -0400 From: Bastian Koppelmann Date: Wed, 31 Oct 2018 14:20:23 +0100 Message-Id: <20181031132029.4887-30-kbastian@mail.uni-paderborn.de> In-Reply-To: <20181031132029.4887-1-kbastian@mail.uni-paderborn.de> References: <20181031132029.4887-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v3 29/35] target/riscv: Remove gen_system() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: mjc@sifive.com, sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de, Alistair.Francis@wdc.com Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org with all 16 bit insns moved to decodetree no path is falling back to gen_system(), so we can remove it. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/translate.c | 35 ----------------------------------- 1 file changed, 35 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 68223925ba..0ff3da641e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -425,34 +425,6 @@ static void gen_set_rm(DisasContext *ctx, int rm) tcg_temp_free_i32(t0); } - -static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc, - int rd, int rs1, int csr) -{ - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); - - switch (opc) { - case OPC_RISC_ECALL: - switch (csr) { - case 0x0: /* ECALL */ - /* always generates U-level ECALL, fixed in do_interrupt handler */ - generate_exception(ctx, RISCV_EXCP_U_ECALL); - tcg_gen_exit_tb(NULL, 0); /* no chaining */ - ctx->base.is_jmp = DISAS_NORETURN; - break; - case 0x1: /* EBREAK */ - generate_exception(ctx, RISCV_EXCP_BREAKPOINT); - tcg_gen_exit_tb(NULL, 0); /* no chaining */ - ctx->base.is_jmp = DISAS_NORETURN; - break; - default: - gen_exception_illegal(ctx); - break; - } - break; - } -} - static void decode_RV32_64C0(DisasContext *ctx) { uint8_t funct3 = extract32(ctx->opcode, 13, 3); @@ -620,7 +592,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn); static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) { - int rs1, rd; uint32_t op; /* We do not do misaligned address check here: the address should never be @@ -629,14 +600,8 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) * perform the misaligned instruction fetch */ op = MASK_OP_MAJOR(ctx->opcode); - rs1 = GET_RS1(ctx->opcode); - rd = GET_RD(ctx->opcode); switch (op) { - case OPC_RISC_SYSTEM: - gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1, - (ctx->opcode & 0xFFF00000) >> 20); - break; default: gen_exception_illegal(ctx); break; -- 2.19.1